Ever since TSMCs Open Innovation Platform (OIP) event, we’ve been hearing all about how the company has qualified its 2.5D chip-on-wafer-on-substrate (CoWoS) process flow, announced its test vehicle, and has begun shipping products. Indeed, at Roadmaps for Multi-die Packaging (November 14, 2012) Jan Vardaman used Altera’s adoption of the CoWoS test vehicle and design guidelines as an example of how the 2.5D era has arrived. But what exactly is CoWoS? What does it look like and how is it different from Xilinx’ technology?
While both Xilinx process and CoWos provide solutions for heterogeneous integration on an interposer for FPGA applications, the CoWoS process flow is completed at the wafer-level, explained Vardaman. CoWoS allows for mixing and matching multiple technologies in a single device, and consolidates manufacturing and assembly to lower risk, achieve optimal yields, and leverage the Cu connection.
The November issue of Solid State Technology features a contributed piece by TSMC’s Jerry Tzou that gives a comprehensive look at the CoWoS process, and talks about progress with the technology so far.
Xilinx has rebranded what was its 2.5D FPGA, now calling it 3D FPGA and 3D ICs. I’ve asked around and have been told it’s really a marketing move, and the the side-by-side partitioned die are still connected to an interposer. So it’s essentially a 2.5D technology that they have re-christened 3D ICs. Max Maxfield, Editor and Chief of All Programmable Planet explains the next generation FPGA 3D ICs here. Essentially, first generation devices use 28nm technology and can be either homogenous or heterogeneous. Second – generation devices will be built on 20nm technology. Maxfield explains that they “will have a variety of homogeneous and heterogeneous configurations. High-growth applications for these little scams include Nx100G/400G smart networks, top-of-rack datacenter switches, and highest integration ASIC prototyping.”
Want to learn more? From December 10 to 14, 2012, Maxfield will be giving a free online course on All Programmable FPGAs, SoCs, and 3D ICs as part of the EE Times University program. You can find all the details here.