Last week I attended SEMICO’s Research Summit, in Scottsdale, AZ, and was fortunate to hear some high-level industry executives discuss the emerging landscape of the semiconductor industry, and 3D integration’s role in it. What was most interesting was the resounding call across the board for collaboration across the supply chain, as well as new approaches to address this new frontier that includes, among other things, 3D IC stacks.

I especially enjoyed the inspirational messages delivered by many of the presenters, encouraging the attendees to embrace  the change and new business models needed to accommodate what Moshe Gavrielov, president and CEO of Xilinx called  “Insatiable bandwidth and ubiquitous computing” of today and tomorrow.  Gavrielov was there to talk about the by now well-known stacked silicon FPGA. He quoted Charles Darwin, saying “it’s not the strongest of the species or smartest who survive, but the one most accepting of change.”  One change to embrace is that of programmable logic replacing ASICS and APPS to accommodate the 50B connected devices expected in the world by 2020.

“We do submicron so you don’t have to,” quipped Joe Sawicki VP and GM, Design-to-Silicon, Division Mentor Graphics, about the Mentor’s approach of driving design tools at the system level. Mentor is a strong supporter of 2.5D approaches such as Xilinx FPGA, and keeping TSVs out of the active area.  He reiterated much of what Wally Rhines said earlier in March at the GSA Memory Conference.  He also supported 3D as an enabler of future scaling, saying that when you consider the cost of the entire system, multi –chip integration results in systems that have better cost performance, and therefore are worth spending money on.

Scaling was further addressed during the panel discussion, moderated by  Mahesh Tirupattur Executive V.P. Analog Bits. Aptly titled, Challenges at 28nm and Below For First-Time Silicon Success, panalists were Chi-Ping Hsu, Ph.D, Senior V.P., Research and Development, Silicon Realization Group, Cadence; Mark Papermaster, V.P., Switching Silicon Technology Group, Cisco; Grant Pierce President & CEO, Sonics; and Suk Lee, Suk Lee, Director, Design Infrastructure Marketing Division, TSMC. The discussion centered on both technology and business challenges of scaling silicon, so I questioned the panel about whether they considered 3D integration an alternative to scaling or a way to scale further. The collective answer was that scaling will continue fundamentally, but 2.5 and 3D offers additional opportunities for system integration – it provides more knobs for designers who can mix and match semi dice. Ultimately, it will not replace scaling altogether.  I found this to be a new twist on the situation, but one that made sense considering the ongoing R&D for EUV lithography and other scaling processes. concurrently with further developments in 3D integration, although it conflicts with the “Scaling is dead” declarations we’ve been hearing on and off in support of industrializing TSVs and 3D stacking.

Addressing the memory wall challenge was Len Perham, president and CEO of Mosys, a company focused on increasing internet performance. (I remembered Len from his days at Optimal and my days at Advanced Packaging).  “Who cares about multicore processors if you can’t manage bandwidth efficiently to get information in and out of a memory or i/o?” he queried. (And that was before Intel announced 22nm 3-D Tri-Gate transistors that are expected to improve performance at a lower power. I wonder if this announcement further strengthens the case for 3D ICs?) Perham said this increased need in bandwidth and access means “the end of parallelism; the future is serial.”

While none of the presentations were focused on 3D integration specifically, it was interesting to note that it is now included in the toolbox with all the other various solutions being discussed to solve some of the same issues.  The recurring theme of collaboration across the supply chain, and the idea that we are indeed treading into a new frontier, because as Danny Birin, Senior V.P. of Altera so succinctly put it, the lines are blurring, and “historical definitions are becoming meaningless.” Indeed, it’s creating challenges for market research when asked to compare 3D (and other innovations) to past technology evolutions.  Birin’s sage advice: shed worn out traditions, rethink priorities and needs, and rethink your development organization, and skill sets.  Let the product drive the structure of organization and design methodologies.  Engage with platform vendors early on in the process – don’t make assumptions of what can or can’t be done.  Don’t pre-assume capabilities.  The goal is to ensure you get the best combination of flexibility, time-to-market, performance, and cost.

Looks like it’s time to hook up the covered wagons and go stake your claim, wouldn’t you say? – F.v.T.


Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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