Laura Rothman Mauer, CTO, Precision Surface Processing
Veeco Instruments Inc.

Over the years, the semiconductor industry has relentlessly focused on shrinking gate dimensions to drive performance. This focus has now transitioned to the packaging side as customers are shifting from wire bonding to flip chip for use in wafer level packaging (WLP). According to VLSI Research, about 35% of chips are currently packaged using WLP techniques. Advanced packaging opportunities slowed in 2017 as customers temporarily delayed adoption of alternative methods such as fan-out wafer level packaging (FOWLP) in favor of cheaper flip chip solutions. While the majority of advanced packaging still revolves around the flip chip technology, FOWLP, and 3D IC packaging are gaining momentum (Figure 1).

Figure 1: Silicon demand for advanced packaging.

Higher performance and shrinking form factors are the drivers behind these advanced packaging methods. The end devices, whether smartphones or high-end servers require superior processing speeds, higher I/O density, and thinner form factors. To enable these characteristics, the technical requirements for the packaging process flow are becoming more challenging.

The basic interconnect and bumping process flow is as follows: barrier/seed layer deposition, patterning, plating, photoresist (PR) strip, and etch (Figure 2). Designers are increasingly using redistribution layers (RDL) in flip-chip designs to redistribute I/O pads to bump pads without changing the I/O pad placement. And under bump metallization (UBM) enhances package reliability needs by providing the critical interface between the metal pad of the IC (or the Cu or Al trace) and the solder (or gold) bump.

advanced packaging
Figure 2: Advanced packaging process steps.

The drive to higher I/O density with improved reliability and performance is leading to a general trend of shrinking line/space geometries along with smaller bump diameter and pitch. Line/space dimensions are moving from greater than 10µm to 2µm while the bump diameters may go down to 10µm in the near future. This presents challenges for the lithography steps as well as the PR strip and UBM/RDL etch steps. This article focuses on PR strip and UBM/RDL, while lithography issues in advanced packaging will be discussed in Part II of this series.

PR Strip: As dimensions shrink and density increases, the photoresist becomes more difficult to remove from the feature.  In the PR strip process, the solvent diffuses into the resist, swells the resist, and then eventually the resist is removed. As dimensions shrink, the ability for the solvent to penetrate the resist is restricted, thus hindering strip efficiency. Longer spray times are required to achieve good photoresist removal, which impacts throughput. An effective way to solve this issue is to use a unified approach, such as Veeco’s ImmJET™ technology, which uses a proprietary method to prepare the wafers for a more efficient removal of the resist in the high-pressure spray station.

Each wafer is immersed under precisely controlled conditions in a heated, recirculating, solvent bath with a nitrogen environment. Sequencing is based on the downstream process times, ensuring each wafer is immersed for an equal length of time. With the appropriate selection of chemistry for the composition and thickness of the dry film, the immersion time allows for swelling and dissolution of the highly cross-linked resist.  Following the immersion step, the surface of the wafer remains solvent-wet during transfer to the single-wafer spin process station. The use of a high-pressure chemical fan spray enhances the removal of residuals, ensuring a clean, resist-free surface. The wafer is then transferred to a spin-rinse-dry station where the surface is completely cleaned.

UBM/RDL: Shrinking line/space dimensions pose a similar challenge in UBM/RDL etch processes. A critical requirement for these seed layer etch steps is to minimize undercut while still removing the barrier and seed layers. Higher undercut impacts the mechanical integrity of the device, while insufficient removal leads to poor device yield. With larger-sized features, the impact of undercut is less since the undercut comprises a small fraction of the feature diameter. If the features shrink from 10µm to 1µm, the same undercut will have an impact that is ten times greater.  To minimize these over-etching issues, better process control is needed to accurately detect when the etch step is complete, resulting in less undercut and maintaining the critical dimension (CD) of the feature (line or bump).

Since wet etching is an isotropic process, the lateral etch will be equal to the vertical etch. To minimize the undercut, the etch process must be stopped when the thickness of the metal has been reached. A migration to single-wafer wet processing is occurring to provide better control of the etching process compared with batch processing in a wet bench, by etching one wafer at a time. The use of endpoint detection (EPD) provides in-situ adaptive process control for determining the exact endpoint for the metal-etch process. Etch uniformity across the wafer is improved by precisely controlling the dwell time of the chemical dispense.

The trend towards more advanced packaging is clear. Market trends continue to be heavily influenced by the need for enhanced mobility and connectivity, automotive electronics including automated driver assistance systems (ADAS), data processing, 5G infrastructure deployment, and increasing functionality in smartphones and other mobile devices. The devices needed to support these future trends will require better performance and reliability within even smaller form factors. While advanced techniques such as FOWLP and 3D integration comprise less than 10% of the market today, they are predicted to grow at over 15% CAGR over the next few years. The manufacturing base will need to be ready, with many customers already actively transforming their methods and strategies to address these advanced packaging challenges by evolving their current process flows and equipment.


The author, Laura Rothman Mauer, would like to thank her co-author, Anil Vijayendran, VP of Marketing, Precision Surface Processing, Veeco Instruments Inc. for his contributions to this article.

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