Warpage Issues in Fan-Out Wafer Level Packaging

Warpage Issues in Fan-Out Wafer Level Packaging

As you all know, warpage is a critical issue for fan-out wafer/panel level packaging. Many people like to talk about it, however, most of them don’t know what they are talking about. Let’s use the chips first, face-up fan-out wafer level packaging (FOWLP) approach as an example. Also, let’s consider three redistribution layers (RDLs). The process flow is schematically shown in the figure below.¹ In this case, there are at least 6 different warpage issues affecting the FOWLP process.

 

The first warpage issue happens right after post mold cure (PMC) of the reconstituted wafer.² If the warpage is too great, then the reconstituted wafer cannot be placed on the back grinding equipment so the back grinding of embedded mold compound (EMC) can be performed to expose the Cu contact-pad.

The second warpage issue happens right after the back grinding of the EMC to expose the Cu contact-pad.² If there is too much warpage, then the reconstituted wafer cannot be placed on the RDL equipment such as the stepper, lithographic, physical vapor deposition (PVD), electrochemical deposition, and etching tools.

The third warpage issue happens right after the fabrication of the first RDL. (The temperature of the PVD is about 200°C, so there is a thermal expansion mismatch among the EMC, Si chip, and glass carrier.) If there is too much warpage, then there are issues in making the second RDL.

The fourth warpage issue happens right after the fabrication of the second RDL. If there is too much warpage, then there are issues in making the third RDL.

The fifth warpage issue happens right after the fabrication of the third RDL. If there is too much warpage, then there are issues (such as holding the reconstituted wafer on the equipment and controlling the accuracy of ball drop during solder ball mounting.)

The sixth warpage issue happens right after the solder ball mounting. (The temperature of the lead-free reflow temperature is about 250°C, so there is a very large thermal expansion mismatch among the EMC, Si chip and glass carrier.) If the warpage of the diced individual package is too great, then there are issues (such as the solder joint standoff height variation, stretched solder joints, and titled component) in printed circuit board (PCB) assembly.

What are the maximum allowable warpages? The rule of thumb is for a 300mm reconstituted wafer, the maximum allowable warpage of the first 5 kinds of warpage is 1mm, but 0.5mm is preferred for high yield. The maximum allowable warpage of the individual package (≤ 20mmx20mm) is 0.2mm, but 0.1mm is preferred for high yield. 

[1] Lau, J. H., N. Fan, and M. Li, “Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging”, Chip Scale Review, Vol. 20, May/June 2016, pp. 38-44.

[2] Lau, J. H., et al., “Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging”, 2017 ECTC Proceedings, pp. 595-602, also, accepted to be published in the IEEE Transactions on CPMT.

  • Mayson Brooks

    Given these warpage issues, what method do you recommend to measure the warpage?

    • Guillou

      Dear Mayson,
      UnitySC with its TMap Series and their TMap Fan-Out solution are able to measure warpage of such rebuilt wafers.

    • Francoise von Trapp

      HI Mayson, On behalf of John Lau, here is his answer:
      There are many methods to measure the warpage. However, for the range of FOWLP warpage, I would like to recommend the “Shadow Moire” method.

  • GaryHuang

    CTE mismatch is mostly caused by apply the heat onto homogeneous materials or hybrid structures . The typical heating method ( convection or conductive ,such as reflow or TCB) cannot help but only the novel heating method can.