Are Glass Substrates the Next Option for Fan-out Packaging?

Are Glass Substrates the Next Option for Fan-out Packaging?

As you all may know, in most fan-out wafer level packages (FOWLP) such as embedded wafer level ball grid array (eWLB) by Infineon and STATS ChipPAC, and TSMC’s integrated fan out (InFO), the chip(s) are embedded in epoxy molding compound (EMC). Additionally, in some fan-out panel-level packaging (FOPLP) such as those being built by Fraunhofer IZM and J-Devices, the chip(s) are embedded in EMC. Other companies, such as AT&S, Unimicron, and Imbera, are embedding chips in a laminate organic substrate.

In my opinion,  in general, chips that are embedded in a laminated organic substrate cannot be larger than 5mm x 5mm, due to the thermal expansion mismatch between the silicon chip (2.5×10-6/oC) and the organic substrate (15×10-6/oC – 18×10-6/oC). 

On June 28, 2013 (priority date: March 5, 2013), Maxim Integrated filed a patent (US 20140252655 A1), for an invention by Khanh Tran, Arkadii V. Samoilov, Pirooz Parvarandeh, and Amit S. Kelkar, “Fan-out and Heterogeneous Packaging of Electronic Components,” proposing to embed the chip(s) in a silicon substrate (Figure 1). A paper was presented during the IMAPS International Conference.

Figure 1: Maxim’s patent drawing for a chip embedded in a silicon substrate.

Again, my opinion is that, in general, the size of the chip cannot be larger than 4mm x 4mm (or the size of the silicon package cannot be larger than 5mm x 5mm). This is because of the thermal expansion mismatch between the silicon (package) substrate (not the chip) and the PCB (18×10-6/oC).

On May 31, 2017, at IEEE ECTC, George Institute of Technology (GIT) will present an alternative to EMC, organic laminate, and silicon, by presenting the very first demonstration of chips embedded in a glass substrate for FOPLP (Figure 2). The paper represents a collaborative effort by GIT, Schott, Asahi Glass Co., Ltd., and DISCO Corporation.

Figure 2: GIT’s fan-out approach with chips embedded in a glass substrate. (L) P&P chips on glass cavities. (R) Chips on glass substrate cavities.

Will this glass fan-out (GFO) technology popular? I cannot tell. But, at least, it adds a new direction in fan-out packaging! ~ J. Lau

  • Ken Kuang

    Nice article!

  • Dev Gupta

    After fumbling around for years trying to push glass as a lower cost replacement for Si in 2.5d interposers, the GIT group seems to have finally accepted its limits ( slower rate in etching TGVs, hence higher cost ) and instead have started leveraging its inherent strengths ( lower tan delta : great for front end in LTE 5, RF does n’t require too many vias ) and the ability to tailor CTE to match various packaging materials ( from Si to organic ) as in the embedded package to be presented at ECTC 2017 ( something like that was done at GE way back in 1990 by Bob Wojnarowski ), but even w/o any embedding glass is a great temporary back up material during processing ( not just 300 mm but at up to panel sizes ), since it reduces warpage during processing, thus enables finer L/S. Coreless substrates processed that way are being used in flip chip packages that give interconnect density, DTR just as good as the much ballyhooed FO WLP but at a lower capital cost. Qualcomm uses it for their latest AP.