Processes and Technology

Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging
2019_01_10_VeecoQ&AHeadshot

Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging

The importance of surface preparation and wafer cleans during semiconductor device manufacturing is migrating from front-end wafer processing to back-end wafer level packaging processes. To get a clearer picture of how this impacts semiconductor equipment and materials suppliers, 3DInCites spoke with Anil Vijayendran, vice president of marketing at Veeco Instruments, Precision Surface Processing D... »

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory
Fig1_final Fig2_final Fig3_final

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory

Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years of progress. Here we look at the dual-gate thin film transistor (DG-TFT), an extremely versatile solid-state data storage device that can be used in monolithic 3D as either a flash memory or a dynamic memory element. It has the potential to provide a path not only ... »

Heterointegration Spoor in the 2015 Analog, MEMS and Sensor Startups to Watch, Part 3
Tube Amp Image NextImage ForceTouch Image 2 Merus Audio Logo Image rcj_Vesper_MEMS_Microphone_package

Heterointegration Spoor in the 2015 Analog, MEMS and Sensor Startups to Watch, Part 3

In Parts 1 and 2 of this series, I drew your attention to what Peter Clarke, writing in EETimes on 02 January 2015, called the “15-in-15: Analog, MEMS and sensor startups to watch in 2015.” If we were to look for heterointegration spoor amongst Peter’s 15 notable startups what would we find? The first “10-in-15” companies profiled in Parts 1 and 2, namely Cambridge CMOS Sensors; Chirp Mi... »

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options
70EFB297-E68C-4726-850D-FB7E324BB93B InvensasBVA3_0

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best performing option at the lowest cost to do the job. However, as performance requirements reach previously un-anticipated levels, pitch requirements become tighter, and density requirements become higher, the job of the packaging engineer to provide increased... »

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction
11235297_s

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally served as a guide for “assessing and improving the future of semiconductor technology,” according to Brian Toohey, president and CEO, Semiconductor Industry Association. Sponsored by five regions of the world including Europe, Japan, Korea... »

Page 1 of 19123»