The 17th Annual Device Packaging Conference (DPC 2021) will be held as an online global event, from April 12-15, 2021. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS). Conference attendees can expect more than 65 on-demand session speakers across three technical tracks and 16 sessions. Recorded technical presentations will be available for on-demand viewing through the Virtual Conference Portal starting April 12. Many of our 3D InCites community members will be participating in DPC 2021 throughout the week via panel discussions, plenary sessions and technical tracks. Here is a list on the agenda:

Live DPC 2021 Technical Panel Discussion

Tuesday, April 13, 2021 | 3:00PM – 4:30PM EST

Electronics Industry Supply Chain: Is it Broken?
Chair and Moderator: E. Jan Vardaman, TechSearch International, Inc. 

Panelists:

Ivor Barber, AMD – Corporate VP Packaging
Veer Dhandapani, NXP Semiconductors – Sr. Director Automotive Package Innovation
Devan Iyer, Technology Management – Educator and Executive Advisor
Rebeca Jimenez, Amkor Technology – Corporate Vice President, Advanced SiP Business Unit
Paul Mescher, Microsoft – Senior Director IC Packaging Technology

Demand for electronic products and services remains strong.  Work-from-home, video conferencing, and remote learning are driving data center growth and laptop and tablet demand. 5G infrastructure rollout is underway and smartphone sales are returning to normal levels. Automotive sales are increasing.  At the same time, the industry is experiencing acute shortages of 200mm fab capacity, components, equipment such as wire bonders, substrates, and lead frames. Is the supply chain broken and what can we do to resolve these issues?

Virtual Global Business Council (GBC) Live Plenary Session

Wednesday, April 14, 2021 | 11 AM – 2 PM EST

Friends in HI Places… Enabling the Transition to Heterogeneous Integration

Advancements in substrates and interconnection will be a key requirement in enabling heterogeneous integration (HI) and the gap between device IO or pad densities and substrate interconnect capabilities is expanding. Substrate technology must transition towards the levels of scaling that the semiconductor industry continues to demonstrate which will require both high levels of innovation and investment.

The industry has been addressing these issues and the urgency for new technologies, solutions and supply chains. These have been highlighted due to ABF and advanced substrate supply shortages. This has created major issues for the industry and the cost/availability and yields for the most advanced fcBGA substrates has become a critical issue.

This Live Virtual Session will Feature 5 Expert GBC Speakers:

  • Bill Chen, ASE Group
  • Bryan Black, AMD
  • John Lau, Unimicron Technology Corp.
  • Jan Vardaman, TechSearch International
  • Santosh Kumar, Yole

Live Industry-Sponsored Panel

Thursday, April 15, 2021 | 1PM – 3PM EST

5G Materials Roadmap: Industry Voices

Among the three industry panelists, Dongshun Bai of Brewer Science will participate in this moderated interactive panel connecting attendees with supply chain solutions and highlights of key technologies their organization can solve, presenting: “Innovation in materials for overcoming technology challenges for heterogeneous integration of 5G devices”

DPC 2021 Professional Development Courses

Monday, April 12th 12pm – 2pm Eastern

Fan Out Variations – Structures and Processes for Low and High Density
John Hunt, ASE Group

Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity. Until around 2016, Fan Out was considered primarily a solution for low-density packaging requirements.

The wide use of mobile and many IoT devices coming into use has driven the need for the increased capability of data centers. Fan Out technology is now in production for many of these applications.  It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5D packaging for these data center requirements. With the advent of chiplet packaging, fan-out also offers a cost-effective solution for this combination of multiple dies in a single package.

We will review how the integration of wafer-level processing technologies and Flip Chip packaging structures have come together into recent advances in both low density and high-density Fan Out packaging. These packages are for automotive, IoT, advanced mobile, and server applications. They can have higher levels of integration and sophistication than has ever been possible in the past. A brief overview of the concept of fan-out packaging and the history of its evolution and fan-out developments to meet both low- and high-end applications will be included in this course.

Tuesday, April 13th
1pm-3pm Eastern

System-in-Package (SiP) – System Solutions Through Miniaturization
Mark Gerber, ASE Group

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system-level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system-level ecosystems to enabling content revenue- a key area of IoT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. This class will also introduce several variations of the SIP platform using Fan-Out Wafer Level packaging and new embedded substrate technologies are also emerging as powerful future platforms to enable lower power and higher performance devices using solderless interconnects.

Technical Tracks

3D Integration Track

3D Technology – 2

A Low Tg Bonding Material for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP)
Arthur Southard, Brewer Science, Inc. (Rachel Cartaya, Dongshun Bai, John Massey, Nathan Parker)

Metrology and Validation Methods

Hybrid Metrology Solutions for Monitoring Microbump Process 20micron Pitch and Less for 2.5D and 3D Integration
Priya Mukundhan, Onto Innovation (Manjusha Mehendale, Johnny Dai, Robin Mair, Jay Chen, Andy Antonelli)

3D Application and Design

Heterogeneous IC Packaging,  Options for Optimizing Performance and Cost
Michael Kelly, Amkor Technology (Dave Hiner, George Scott)

Fan-Out Wafer Level Packaging & Flip Chip Track

FOWLP: Technology and Reliability

Setting the 600mm Large Panel Fan-Out Standard with M-Series TM
Clifford Sandstrom, Deca Technologies (Timothy Olson)

New Adaptive Patterning Techniques for the Chiplet Era
Craig Bishop, Deca Technologies (Chris Negrich, Jiyang Zhou, Ryan Bartling)

FO-WLP: Design and Application

Using Deca’s Adaptive PatterningTM to Win the Chiplet Integration Race with Siemens EDA and ASE
Robin Gabriel, Deca Technologies (Jan Kellar, Deca Technologies; Keith Felton, Ian Gabbitas, Mentor a Siemens Business; John Hunt, Lihong Cao, ASE US)

FO-WLP: Equipment and Materials

Chemistry and Process Considerations for the Removal of Residues for Hybrid Bonding
Phillip Tyler, Veeco Instruments (Ian Cochran, Jonathan Fijal, John Taddei, Veeco Instruments; Thomas Workman, Dominik Suwito, Guilian Gao, Gabe Guevara, Gill Fountain, Cyprian Uzoh, Jeremy Theil, Laura Mirkarimi, Xperi Corporation)

A Novel Photosensitive Permanent Bonding Material for Polymer/Metal Hybrid Bonding
Baron Huang, Brewer Science, Inc. (Duo Tsai, Xiao Liu, Rama Puligadda)

Advancements of Temporary Bond and Debond: Creating Photonic Debond Methods and Materials for Wafer-Level Packaging
Luke Prenger, Brewer Science, Inc. (Xiao Liu, Xavier Martinez, Brewer Science, Inc.; Vikram Turkani, Vahid Akhavan, Kurt Schroder, NovaCentrix, Inc.)

Improving Seed Layer Adhesion and Reliability Through RIE Pretreatment
Mohamed Elghazzali, Evatec AG (Roland Rettenmeier)

Active Mold Packaging for Novel RDL Formation in a Fan-In Ball Grid Array for Power Applications
David Lee, Azimuth Industrial Company Inc. (Florian Roick, LPKF Laser & Electronics AG; Richard Retallick, MacDermid Alpha Electronics Solutions; Masaru Endo, Sumitomo Bakelite Co., Ltd.) 

Flip Chip: Design, Process, and Reliability

High Thermal Performance TIM (Thermal Interface Material) for Lidded FCBGA Products
YoungDo Kweon, Amkor Technology Inc.Process Control Methods and Applications of In-line

Automatic X-ray Inspection in High-volume Manufacturing
Brennan Peterson, SVXR Inc.

Challenges for Achieving Automotive Grade 1/0 Reliability in FCBGA and fcCSP Packages
Knowlton Olmstead, Amkor Technology, Inc.

Advanced Packaging & Emerging Materials for Automotive, 5G & Next-Gen Applications Track

Automotive Applications – Advanced Packaging and Test- Session 1

Chip Scale Power Transistor Packaging
Shaun Bowers, Amkor Technology, Inc.

Power Packaging Trends in Emerging 48V Ecosystem
Ajay Kumar Sattu, Amkor Technology, Inc.

Automotive Applications – Advanced Packaging and Test- Session 2

Design of Subsystem Module Package for Power Distribution Network
HoJeong Lim, Amkor Technology, Inc. (Ruben Fuentes)

Automotive Applications – Advanced Packaging and Test- Session 3

Advanced Materials for Automotive SiP Applications
Ken Araujo, NAMICS Corporation

Automotive Applications – Advanced Packaging and Test- Session 4

A Viable Copper Based Alternative to Palladium Activation Systems for Electroless Copper Processing
Roger Massey, Atotech Group (Laurence Gregoriades, Stefan Kempa, Andreas Kirbs, Josef Gaida, Julia Lehmann

Analysis and Management of the Effects of Fluorinated Gases during Plasma Dicing
Richard Barnett, SPTS Technologies Ltd. (Janet Hopkins, Samira Kazemi, Oliver Ansell, Simon Dawson, Matthew Day, SPTS Technologies Ltd.; David Parker, STMicroelectronics

5G Applications – Advanced Packages, Processes and Materials

Thermal Performance Enhancement of Dual Side Molding SiP Module for 5G Application
Hung-Hsien Huang, ASE Group (Wei-Hong Lai, Ian Hu, JimDL Chen, David Tarng, CP Hung)

VIAFFIRM™ Thin Glass Handling Technology
Aric Shorey, Mosaic Microsystems (Shelby Nelson, David Levy, Paul Ballentine)

Trine Pierik

Trine Pierik is the 3D InCites community membership director. She is responsible and committed to…

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