SPTS

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in mold wafers, thereby enabling the latest generation of ultra-thin w... »

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

“It is better to be first than it is to be better.” (Ries and Trout, in The 22 Immutable Laws of Marketing.) Or is it “Fast Followers Not First Movers Are The Real Winners?” Fan-Out Wafer Level Packaging has built up such a head of steam this year (see “iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform”) that backwards reels the mind thinking about what come... »

SPTS sees a Brighter 2016

SPTS sees a Brighter 2016

In contrast to some of the gloomier predictions of the analysts, we think 2016 will be a growth year for our business. In packaging, we see a number of development projects moving into production this year, and a raft of makers adding capability to catch up with the early adopters. The major example will be the growth of fan-out wafer level packaging (FOWLP). After six years of being a niche acti... »

In Conversation with Yann Guillou About the SEMI European MEMS Summit 2015

In Conversation with Yann Guillou About the SEMI European MEMS Summit 2015

Yann Guillou, Membership & Business Development, SEMI Europe, talked with 3D InCites / 3D+ about the upcoming European MEMS Summit 2015, which will be held in Milan, Italy, on 17-18 September. 3D InCites / 3D+: Yann, thank you for taking the time to talk with us today about the European MEMS Summit 2015 SEMI is producing this year in Milan. You have as a theme for the summit Sensing the Planet... »

SPTS Technologies Receives Supplier Excellence Award from Analog Devices

SPTS Technologies Receives Supplier Excellence Award from Analog Devices

YAVNE, ISRAEL, April 20 2015 | ORBOTECH LTD. (NASDAQ: ORBK) today announced that SPTS Technologies, an Orbotech company and supplier of advanced wafer processing solutions for the global semiconductor and related industries, was presented with a Supplier Excellence Award in the ‘Special Achievement’ category at the Analog Devices (NASDAQ: ADI) annual award ceremony held in Hong Kong. The ADI S... »

Riding Out on a Horse and in on a Goat: 3D IC Predictions for MEMS

Riding Out on a Horse and in on a Goat: 3D IC Predictions for MEMS

The Lunar New Year is soon upon us, and we will be celebrating the Year of the Goat with firecrackers, red packets (I hope!), and the evening parade in San Francisco on 07 March 2015. The goat is a sturdy animal whose praises are often undersung. Undersung – that sounds a little bit like the MEMS Industry, which, as I wrote in 2014, is sometimes looked upon as being the poor cousin of the se... »

Semiconductor Equipment Manufacturer Consolidation Update

Semiconductor Equipment Manufacturer Consolidation Update

It was a much-talked-about topic this year at SEMICON West 2014 (SW2014) – this trend of semiconductor equipment manufacturer consolidation. Just in the past year, we’ve read the headlines about Applied Materials (AMAT) and Tokyo Electron ‘s (TEL) impending merger; LTX Credence’s acquisition of Multitest, Everett Charles, Technologies and atg Luther & Maelzer businesses from Do... »

Having the Courage to Design in 3D TSVs

Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and that of David Butler, SPTS, once again reinforced wha... »

SPTS Technologies and CEA-Leti / Nanoelec RTI collaborate on 3D TSV Technology

SPTS Technologies and CEA-Leti / Nanoelec RTI collaborate on 3D TSV Technology

Leading Semiconductor Equipment Maker and Renowned European Research Institute to Collaborate in Advanced Packaging Technologies under the Framework of Nanoelec RTI Newport, United Kingdom – June 24, 2014 – SPTS Technologies, a leading manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti... »

Fine Tuning Processes for TSV Reveal

Fine Tuning Processes for TSV Reveal

Through silicon via (TSV) reveal is a critical part of the wafer-thinning step in 3D IC backside processing, where the wafer is thinned to expose the Cu “nails” that ultimately form the interconnect between die stacks. Some of the risks involved in this step include backside contamination (Cu diffusion) due to premature contact with the vias. Poor via fabrication depth uniformity can also cont... »

Page 1 of 3123