Virtual IWLPC kicks off on October 13, 2020, and 3D InCites community members will be well represented, from the panel discussion to the exhibit hall, to the program.
The Virtual IWLPC panel discussion titled “Meeting Future Advanced Packaging Challenges: What’s Next?” will commence on Wednesday, October 14, 2020, at 9:00 am US Pacific Time.
The panel will discuss challenges and possible solutions to advancements in heterogeneous integration, high-density substrates, and Fan-Out Wafer-Level Packaging (FO-WLP) as they impact the material selection, design, and fabrication of features, inspection, test, and reliability. Attendees will be able to submit questions and get responses in real-time from the expert panel.
Panelists include Tim Olson, Deca; Tanja Braun, Ph.D., Fraunhofer IZM; Rahul Manepalli, Ph.D., Intel Corporation; Max Min, Ph.D., Samsung Foundry; and Shin-Puu Jeng, Ph.D., TSMC. The panel is moderated by E. Jan Vardaman, TechSearch International, Inc.
The panel discussion is open to all registered attendees. The technical conference and expo are available on-demand from October 13-30 with a live, online exposition enabled October 13 and 14. Details are available on the website. Following is a list of 3D InCites member companies exhibiting and/or speaking at the event.
Virtual IWLPC EXHIBITOR PREVIEWS
Solutions for System-in-Packaging (SiP) and Board Level Underfills (BLUF)
Demand for today’s semiconductor packaging is pushing towards the heterogeneous integration of different devices and technologies. The goal for next-generation modules is to offer improved performance with lower power consumption while moving towards miniaturization. NAMICS offers a diverse suite of innovative solutions to handle these upcoming package challenges, such as an increase in thermal dissipation, small form factor, protection from RF interference, and high reliability to meet future automotive applications.
In addition, the latest board-level underfills from NAMICS are designed to meet a diverse number of both current and future applications. Its innovative board level underfill is formulated for today’s packaging designs and comply with the future REACH 2022 requirements.
ERS supplies the advanced wafer-level packaging market with its fully automatic, as well as manual, debonders and warpage adjust tools used in the production of both 200mm and 300mm eWLB device packages. On a broader scale, ERS supports not only eWLB but many other Fan-Out Wafer-Level-Packaging (FOWLP) and Panel-Level-Packaging (FOPLP) technologies. ERS will be showcasing its debonding and warpage adjustment technology as well as its manual debonding station specifically designed for research and development laboratories or pilot lines during the ramp-up of new technologies. The ERS MPDM700 System is ideal for the separation of the panel from its carrier related to the FOWLP technology. The system offers high repeatability of results with respect to the quality of the debonded wafer.
Micross is the global one-source provider of IC packaging solutions to serve customers’ complete packaging, assembly, and test needs. Its advanced packaging and 3D integration solutions enable higher-performance systems with decreased size, weight, and power (SWaP). Micross AIT offers access to our 2.5D/3D technology platform through joint development projects, prototyping services, and small volume production.
SVXR is a pioneer in the development and deployment of fully automatic fast inline X-ray inspection solutions utilizing the latest Artificial Intelligence (AI) and Machine Learning (ML) methodologies. Its innovative High-Resolution Automatic X-ray Inspection (HR-AXI) delivers front-end wafer fab-like inspection techniques to the advanced packaging industry.
Xperi will be showcasing its DBI® Ultra, an enabling low-temperature, low profile die to wafer and die to die hybrid bonding technology platform. By eliminating the need for copper pillars and underfill, DBI Ultra can enable a dramatically thinner stack than conventional approaches. DBI Ultra also allows the stacking of die that are the same or different sizes, processed on fine or coarse wafer process technology nodes, or manufactured on the same or different wafer sizes while readily scaling down to 1 µm interconnect pitch providing the ultimate 2.5D and 3D integration flexibility.
Visit TechSearch International to find out more about its advanced packaging market and technology trends reports. Its Advanced Packaging Update features special coverage of market and technology developments for BGAs, CSPs, stacked die CSPs, flip chip, and wafer level packages. Each issue includes new applications, developments in materials and assembly equipment, and new package constructions.
TechSearch International also recently began performing teardowns of leading-edge and prominent system products, including smartphones from Samsung, Apple, and Huawei, smartwatches such as the Apple Watch, and consumer electronics including the Ring Video Doorbell and Nest Learning Thermostat. Teardowns from TechSearch International focus on the advanced semiconductor packaging aspects of the systems.
EVG’s Heterogeneous Integration Competence Center is designed to assist customers in leveraging EVG’s process solutions and expertise to enable new and enhanced products and applications driven by advances in system integration and packaging. These include solutions and applications for high-performance computing and data centers, the Internet of Things (IoT), autonomous vehicles, medical and wearable devices, photonics, and advanced sensors.
EVG wafer bonding systems can be configured for R&D, pilot-line or high-volume production, and for any direct or interlayer-based bonding process, including sophisticated low-temperature covalent bonding. With this portfolio of technologies and equipment, EVG addresses markets for advanced packaging and 3D integration, MEMS, as well as advanced compound semiconductor and SOI substrates, holding the leading position and dominant market share.
EVG’s wafer-level optics (WLO) manufacturing solutions enable a multitude of novel optical sensing devices for mobile consumer electronics products. Key examples include 3D sensing, biometric authentication, environmental sensing, infrared sensing, and microlens arrays. Other applications include automotive front-lights, light carpets, optical diffusers, and medical imaging.
Virtual IWLPC Technical Program Speakers
#172: Design Process & Methodology for Achieving High-Volume Production Quality for FOWLP Packaging
Keith Felton & John Ferguson
Advanced high-density packages such as high-density Fan-Out Wafer Level Packaging (FOWLP) bring design challenges that traditional organic laminate processes and design tools struggle with and often fail to satisfy. This paper will discuss the process and design flow Mentor developed through partnerships with leading foundries and OSATs that are now driving high-volume production. The goal of this paper is to provide real-world experience, observations, guidance, and recommendations for package designers embarking on the design of high-density Fan-Out Wafer Level Packaging (FOWLP) packages.
#179: Maskless Lithography Optimized for Heterogeneous and Chiplet Integration
Moving from monolithic to the second and to the third dimension is becoming increasingly important within the industry. Heterogeneous and chiplet integration making use of advanced packaging technologies has increased in complexity over years as well as in a number of options. Higher performance, higher bandwidth, and lower power consumption requirement drive the approach toward 3D integration, whereas the need of finer RDL line/spacing, as well as smaller µbumps and µpillars critical dimension, delineates integration design rules at package and substrate level too. The importance of design flexibility and the ability not only to adopt both die- and wafer-level designs simultaneously but also the viability of fast tapeout changes is addressed in order to cover the scope of application for a wide range of packaging technologies.
#182: Physical Verification of Panel-Level Packaging Designs Utilizing Adaptive Patterning Technology
One of the historical barriers to the broad adoption of fan-out wafer or panel-level packaging has been yield loss associated with ‘die drift’. Deca has introduced a novel technology that breaks through the historic die drift barrier called Adaptive Patterning™. Within Adaptive Patterning, every device has a unit-specific pattern applied which perfectly aligns the fab build-up dielectric and metal layers with the actual ‘drifted’ device position with the package. Deca and Mentor, a Siemens business have collaborated to improve the Calibre technology so that it supports the Adaptive Patterning technology for M-Series fan-out panel level packaging while keeping a reasonable TAT for panel sign off.
#220: Optimizing X-Ray Inspection for Advanced Packaging Applications
Brennan Peterson, Ph.D.
The advanced packaging industry continues to grow: Demands on bandwidth and device integration lead to increased package density and dramatically increased device pin counts. And the ever-increasing ubiquity and criticality of device also increase the demands on reliability. These trends together create the need for new strategies in advanced packaging metrology, inspection, and control. SVXR has developed both advanced x-ray inspection (AXI) hardware and software tools that allow inspection at part per million defect rates, and allow cost effective control strategies. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year. An overview of reliability sampling challenges as it relates to end of line inspection as well as sampling for both defect type and incidence is critical to understanding how and what to measure.
#221: Different Layout Fan-out Panel Level Package (FOPLP) Warpage Profile Handling on Large Area Thermal Chucks
Debbie-Claire Sanchez, P.E.
Complexities in IC application and aim for miniaturization has put fan-out package into the limelight. Several advantages have been noted for the fan-out structure including high electrical and reliability performance, enabling multi-die configuration for 2.5D and 3D application allows the packaging of a high-density chip as well as allowing less than 5um line/space RDL traces. These advantages came with a cost that the industry wants to cut down. To address this need, the idea of large area packaging has come-up. However, the fan-out structure commonly encounters two main issues; die shift and warpage. This presenation aims to show how to handle different warpage profiles of the panel during heat treatment to reduce downtime impact on the manufacturing line.
#222: Bringing New Life to Glass for Wafer-Level Packaging Applications
Rafael Santos, Ph.D.
Glass is not a new material for Wafer-Level Packaging (WLP) applications and technologies, however, its use is still very limited. Despite its low material cost and incredibly interesting properties, traditional glass microprocessing technologies inevitably increase its cost while negatively affecting the characteristics of glass that made it initially interesting.
Laser-Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics, that enables highly precise and reliable micro featuring of glass. In this work, we will show how LIDE® unlocks the use of glass for RF applications by taking full advantage of fused silica’s low transmission loss and by enabling the creation of metalized paths in glass connected to through glass vias (TGV).
#360: Optimization of Low-Temperature PECVD Dielectric Stacks for Via-Reveal Passivation
Keith Buchanan, P.E.
Advanced packaging technologies, incorporating through-silicon vias (TSVs) have the potential to improve functionality and electrical performance of semiconductor devices in reduced package size. In this work, we show how low-temperature PECVD dielectric passivation stacks formed using SiN and TEOS SiO can be engineered to provide an optimal combination of step coverage, tuned stress, passivation performance and electrical isolation. Crucially, electrical properties and stack stress are shown to be stable with no moisture absorption or drift in film properties over time when exposed to the atmosphere.
#363: Die to Wafer Hybrid Bonding: Multi-Die Stacking with TSV Integration
Guilian Gao, Ph.D.
The direct bond interconnect (DBI®) Ultra technology is a low-temperature die to wafer (D2W) and die to die (D2D) hybrid bonding technology that solves many challenges with pitch scaling in advanced packaging. The ability to scale to less than 1 µm pitch, to maintain throughput comparable to mass reflow flip-chip, and to provide improved reliability performance makes this platform technology worth considering for the next generation packaging in the semiconductor industry. The two application areas which will benefit significantly in the migration from Cu µbump or Cu pillar to an all-Cu DBI are high bandwidth memory (HBM) and compute-intensive applications in 2.5D integrated solutions. A critical enabler of the DBI Ultra for manufacturing is the availability of suitable pick and place bonders. We have fabricated a test vehicle with TSVs similar to an HBM DRAM footprint to build 4-die stacks to demonstrate the DBI Ultra technology. We will share the electrical yield of the 4 die stacks with TSVs in this paper.
#366: Through Glass Vias using an Industry Compatible Glass Handling Solution
David Levy, Ph.D.
Thin glass (< 200 μm) has ideal properties for electronic packaging and RF applications. In electronic packaging, a smooth, dimensionally stable surface allows high-resolution line/space patterning, while through glass via (TGV) technology permits integration in many relevant packaging structures. These capabilities combine with low loss tangent at microwave frequencies and robustness to temperature and humidity to yield high performance for RF applications. We discuss a thin glass handling solution coupled with recent innovations that give glass an entry point into these applications at a large scale using the existing fabrication infrastructure. We also describe the formation and metallization of TGVs utilizing our proprietary process. When using silicon as the handle substrate, vias in the glass terminate on the silicon and are thus are comparable to blind vias in silicon. We discuss the ability to make tapered TGVs while tuning their size and via profile, as well as results in metallization to produce fully filled, void-free vias using a range of seed and plating approaches.
#370: Active Mold Packaging for Novel Antenna-in-Package Interconnection and Manufacturing
IC package designers wishing to benefit from space saving Antenna-in-Package (AiP) technologies rely on an intricate selection of materials and interconnect processes to produce a self-contained integrated module. This paper presents a new way to reduce the production complexities of AIP by introducing a novel homogeneous packaging technology: Active Mold Packaging (AMP). Active Mold Packaging directly establishes electrical connections, such as patch antennas, signal vias, and Electro-Magnetic-Interference (EMI) shields for RF applications on the surface and in the volume of the encapsulating Epoxy Mold Compound (EMC). Advancing the development of multifunctional compact devices, AMP in essence transforms the passive and undeveloped real-estate of the EMC into an active carrier of package functionality.