Latest Posts
IFTLE 444: Chip on Interposer on Substrate vs High Density Chips-Last Package Cost Modeling
This year’s SEMI 3D & Systems Summit was held in late January in Dresden. In the next few blogs, we...
IFTLE 443: Controlling Warpage and Placement Error for FOWLP
In the Jan/Feb issue of ChipScale Review, there were two interesting articles on fan-out wafer-level packaging (FO-WLP) entitled “Eliminating Warpage...
IFTLE 439: imec’s Flip Chip on FOWLP… a Closer Look
3D InCites presented the 2019 process of the year award to Eric Beyne and Arnita Podpod of IMEC for their...
IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller
There are several different fan-out wafer-level packaging (FOWLP) technologies that are currently in high-volume production. The traditional fan-out (FO) technology...
TechSearch International Analysis Predicts Growth for Fan-in WLP and FO-WLP
TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan-out WLPs (FO-WLPs). Despite lower growth for...
Book Review: Advances in Embedded and Fan-out Wafer Level Packaging Technology
When asked by Beth Keser and Steffen Krönert to review their new book, Advances in Embedded and Fan-out Wafer Level...
Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging
As the semiconductor industry shifts focus from CMOS scaling to heterogeneous integration, the importance of surface preparation and wafer cleans...
IFTLE 409: ST Micro Studies Hybrid Bonding Reliability; TSMC 2019 Packaging Revenue
Continuing our look at the 2019 SEMI 3D and Systems summit in Dresden, we look at presentations on advanced packaging...
Advanced Packaging: Game Changer for Semiconductor Revolution
Advanced packaging has entered its most successful era boosted by a need for better integration, the end of Moore’s law...
IFTLE 404: One Micron RDL; FOWLP Die Shift; Antennas for FOWLP
In this IFTLE post, we continue our look at presentations from the 2018 EPTC Conference… Ultratech / IMEC / JSR...
Unisem Advanced Technologies Selects Two Veeco Tools to Support Expansion of Fan-out Wafer-level Packaging Portfolio
Veeco Instruments Inc. (Nasdaq: VECO) announced today that Unisem Advanced Technologies Sdn Bhd (UAT) has purchased Veeco’s WaferStorm® single wafer...
IFTLE 398: Samsung’s 256Gb 3DS (TSV-Stacked) RDIMM; IMAPS 2018 in Pasadena
Samsung at the Leading Edge At the recent Samsung Tech Day, the company unveiled several new technologies: Their 7nm extreme ultraviolet...
Talking Nerdy with Exhibitors at IWLPC 2018
With heterogeneous integration, 3D, and advanced wafer-level packaging technologies officially declared the rising stars of the semiconductor industry, materials, process...
Bridging the Interconnect Pitch Gap Calls for 3D Technologies
Last week at IWLPC, keynote speaker, Doug Yu, TSMC, kicked off the event with a similar storyline used by ASE’s...
Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging
Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level...
Transforming the Fan-out Landscape
These days, the first thing that comes to mind when someone mentions fan-out (FO) technology is Apple’s A10 processor built...
TechSearch International Analyzes Trends in FO-WLP including Panel Activity
While Apple remains the main customer for TSMC’s Integrated Fan-Out WLP (InFO-WLP), an increasing number of companies are adopting a...
There’s a Fan-out for That
Long gone are the days of the “killer app” and the notion that a single device market like personal computers...
