Processes and Technology

Latest Developments in Cleans for TSVs and Cu Bumps
50micronbump

Latest Developments in Cleans for TSVs and Cu Bumps

At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on new developments in cleans for TSVs and Cu bumps for 2.5D and 3D IC processes. Cleans has become increasingly important as bump pitches are reduced and TSVs have higher aspect ratios. It’s not just about being clean enough, but also about surface preparation for the next proc... »

TCI for Wireless Chip Stacking; Progress for Monolithic 3D

TCI for Wireless Chip Stacking; Progress for Monolithic 3D

Every once in a while, it’s important to remember that through silicon vias (TSVs) might not be the only game in town. While many continue to forge ahead, with commercialization so close we can taste it, others are already moving on to the next thing or looking for alternatives. Will these beat TSVs to the finish line? Not likely, considering this industry’s slow-to-adopt culture. But it’s s... »

Polymer filled TSVs, Courtesy of EV Group
2012_09EVG150

Polymer Filled TSVs: Solving the Cu Stress Issue

I’ve been on a quest to find out more about EV Group’s new polymer filled TSVs since they first announced it in September. According to a company press release, NanoFill™ process is said to provide “void-free via filling of very deep trenches and high-aspect ratio (HAR) structures, and is suitable for all common polymeric dielectrics—offering a highly flexible, low-cost and production-re... »

The Back Story on Besang’s True 3D ICs
BeSang IncProcessflow TRUE3DICvs3DNAND copy

The Back Story on Besang’s True 3D ICs

BeSang Inc, a fabless semiconductor company in Beaverton, OR, has been on my 3D IC radar since 2008, when I first edited a 3D technology cover feature in Advanced Packaging Magazine, written by George C. Riley, that included a status report on BeSang’s TRUE 3D ICs™, which had just been demonstrated. What I didn’t understand then, that I know now, was that this was an example of what we today... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

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