Maskless Lithography Addresses Shift Toward Heterogeneous Integration and 3D Packaging
Moving from 2D scaling to heterogeneous integration and 3D packaging is ever-more critical to improving semiconductor device performance. In recent years, advanced packaging technologies have increased in complexity as well as in variability to support a wider range of devices and applications. In this article, we investigate the limitations of...
Understanding Wafer Applications in Surface Metrology
This detailed blog covers how wafers are manufactured and processed, what makes a perfect wafer, and which surface metrology approaches can be used for quality assurance. First… the manufacturing process Microelectronic components and semiconductors are manufactured on round thin discs, referred to as wafers. Wafers can be made of various...
Contributing to a Greener Semiconductor Industry
Recently we read an interesting article here on 3D InCites about the role secondary markets play in contributing to a greener semiconductor industry. Did you know that the secondary market for semiconductor tools comprises nearly 10% of the overall equipment market? We want to dig a little bit deeper into this topic and...
Electronics Packaging – From Afterthought to Product Differentiator
Electronics Packaging vs. Advanced Packaging Electronics packaging is generally divided into three major areas, traditional packaging – also called standard or mainstream packaging, and sometimes even just “Others”: advanced packaging and emerging packaging technologies. Traditional packaging is everything with wire or ribbon bond interconnects on a ceramic, metal lead frame,...
Hybrid Bonding Bridges the Technology Gap
A Technology Chasm Until recently, the world of IC fabrication was neatly divided into the distinct stages of front-end and back-end processing, with a large chasm separating them for both process complexity and economic value. The front end has been focused on increased processing or computing power and achieves this...
Will An Adhesion Promoter Prevent Delamination in Power Semiconductor Packages?
Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is...
Die-to-Wafer Bonding Steps into the Spotlight on a Heterogeneous Integration Stage
The semiconductor industry is currently undergoing the most radical change in its history. Many new applications such as artificial intelligence (AI), augmented/virtual reality, and autonomous driving require enormous computing power with processors optimized specifically for each application. At the same time, development cycles are becoming shorter, costs for new chip...
Novel Approaches to Wafer Handling
Economics are forcing semiconductor manufacturers away from traditional 3D through silicon via (TSV) packaging integration. The future of advanced packaging continues to evolve towards chiplets and innovative new ways to combine specialized microelectronics components. This allows manufacturers to streamline the production for individual “subassemblies” that can then be configured later...
Fine-Pitch 3D Stacked Technologies for High-performance Heterogeneous Integration and Chiplet-based Architectures
3DIC Integration using 3D stacked technologies in its true definition has a long history.1 Richard P. Feynman expressed this vision in 1985: “Another direction of improvement of computing power is to make physical machines three-dimensional.”2 Successively, several research and development (R&D) initiatives started world-wide. In the late 1980s, in a...
What Does Panel-level Packaging Mean for Seed Layer Deposition?
Seed layer deposition is one of the most critical process steps in manufacturing vertical and horizontal interconnects. At the panel level, seed layer deposition must deliver high-performance degas, etch, and sputter deposition processes as well managed substrate temperature throughout the whole process to ensure low contact resistance (Rc) and excellent...
Increasing the Conductive Density of Power Packaging
March 3, 2021 – Wide bandgap (WBG) semiconductor technologies have created new challenges and opportunities for power packages. Developments such as silicon carbide (SiC) and gallium nitride (GaN), have a higher figure of merit (FOM) compared to silicon MOSFETs and have extended the efficiency, output power and/or switching frequency range...
3D: The El Dorado of Heterogeneous Integration
From the cloud to edge computing, the quest for ever-greater power efficiency remains researchers’ top priority. From high-end niche to mass-market applications, the best cost-to-performance tradeoff is key to providing a competitive advantage. While Moore’s Law has helped meet the performance required in terms of data transfer and power efficiency...
CEA-Leti/Intel Collaboration brings 3D Powerhouses to the Advanced 3D Packaging Table
CEA-Leti and Intel recently announced a new collaboration effort on advanced 3D packaging technologies for processors to advance chip design. The research focuses on the assembly of smaller chiplets optimizing the interconnect technologies between the different microprocessors and on new bonding and stacking technologies for 3D ICs focused on high-performance...
Plasma Treatment During Fan-Out Packaging Maximizes Performance and Optimizes Costs
In recent years, there has been an increased focus on fan-out wafer-level packaging (FOWLP) due to the smaller packaging size requirements for smartphones and handheld electronic devices. FOWLP – and fan-out panel-level packaging (FOPLP) – is the process during which known good dies (KGD) from the original silicon wafer are...
48V Ecosystem and Power Packaging Trends
With each passing year, emerging growth application areas such as Automotive, Cloud Computing, Industrial Automation, and Telecom (5G) Infrastructure are garnering more attention. Although the application segments are different, there is a commonality in how voltage conversion and power distribution are achieved at the system level. System demands are becoming...
Carrier Wafers for Semiconductor and MEMS Manufacturing
As technology rapidly moves forward, the reduction of device and chip size is playing an important role in implementing as many chips and sensors in the smallest space. For this reason, the thickness reduction of semiconductor wafers is necessary. Thin semiconductor wafers (thickness around 50-100 µm) are flexible and fragile....
Temporary Wafer Bonding System Is Based On Electrostatics, Not Adhesives
Temporary wafer bonding is widely employed in semiconductor device fabrication and in semiconductor device packaging applications, particularly now that changes in the Z dimension are calling for thinner and thinner silicon devices, and thinner and thinner packaged devices. This means that wafers and singulated die must be supported through parts...
Temporary Bonding and Mold Process to Enable Next-Gen FOWLP
Temporary wafer bonding processes were initially developed for enabling three-dimensional (3D) stacked integrated circuits (ICs). For example, dies can be stacked on top of each other using die-to-wafer stacking to create 3D IC stacks. Through-Si vias (TSVs) and microbumps are used to interconnect the finished dies. These techniques require the...
A Look Inside The 3D Technology Toolbox For STCO
System-technology co-optimization (STCO) – enabled by 3D integration technologies – is seen as a next ‘knob’ for continuing the scaling path. In this article, we will unravel the STCO principle, open up the 3D technology toolbox and bring up two promising cases: logic on memory, and backside power delivery. After DTCO...
Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging
As the semiconductor industry shifts focus from CMOS scaling to heterogeneous integration, the importance of surface preparation and wafer cleans during semiconductor device manufacturing is migrating from front-end wafer processing to back-end wafer level packaging processes. This, due to a combination of high-reliability applications, such as autonomous vehicles, 5G, artificial...
