Latest Posts
Advanced Packaging – Measuring Deep Etch Trenches
Adoption of advanced packaging is accelerating as the benefit of the classic Moore’s Law transistor shrink diminishes on a monolithic...
Wafer-Level Packaging Is Well-Positioned for Growth
Wafer-level packaging (WLP) saw significant growth in 2021 due in large part to the increased performance needs of data-driven 5G...
ACM Research Launches Its First Plating Tool to Support Wafer-Level Packaging and Plating Applications in Compound Semiconductor Manufacturing
Automated system for flat or notched wafers; multiple orders to ship during third quarter of 2021 Fremont, Calif. – August 25,...
Amkor’s DSMBGA Advanced SiP Platform is the Preferred Packaging for 5G RF
Amkor Technology, Inc. (Nasdaq: AMKR), a leading provider of outsourced semiconductor assembly and test (OSAT) services, is advancing the evolution of...
EV Group Unlocks Agile and Efficient Production Scaling with Next-Generation Step-and-Repeat Nanoimprint Lithography System
EVG®770 NT enables large-area master stamp fabrication of complex micro- and nano-structures for augmented reality waveguides, wafer-level optics and advanced...
Trends in Semiconductor Manufacturing: Wafer-Level Packaging
One of the hottest trends in semiconductor manufacturing today is wafer-level packaging (WLP). According to Allied Market Research, the global...Trymax Wafer Level Packaging DCP™ Plasma Treatment
As semiconductor device manufacturers further shrink the size and increase the reliability of packaging devices, plasma treatment is increasingly used...
Samsung VP to Keynote IWLPC
San Jose, California – USA – The International Wafer-Level Packaging Conference and Expo announces Dan Oh, Ph.D., Engineering VP of...
Micross Raleigh Facility Receives DMEA Microelectronics Trusted Source Certification
Orlando, FL, January 15, 2020 – Micross is pleased to announce that its Advanced Interconnect Technology operation (Micross AIT) located...
IWLPC 2019 Brings You Advanced Packaging in an Interconnected World
Anyone whose anyone with a hand in the evolution of wafer level packaging will be in attendance or exhibiting at...
EV Group Partners with NSI to Enable First Wafer-level Heterogeneous Integration of GaAs on Silicon for RF Front-end Module Manufacturing
EV Group (EVG), a leading supplier of wafer bonding and lithography equipment, today announced that it has partnered with Ningbo...
Why Today’s Advanced Packages Need Better Inspection and What’s Being Done About It
It’s almost ironic. As CMOS scaling (aka: Moore’s Law) has slowed due to the increased complexity and cost of achieving...
The 14th 3D ASIP Conference Addresses a Spectrum of 0pportunities, Part 1
Several years before I started promoting 3D IC benefits in 2008, a small team of industry visionaries founded the 3D...
Rudolph Announces Multiple Customers’ Acceptance of its Firefly Inspection System
Wilmington, Mass. (September 12, 2017)—Rudolph Technologies, Inc. (NYSE: RTEC) announced today that its Firefly™ Inspection Systems, shipped to fulfill previously...
Pasadena offers Roses and Technology
California’s Pasadena is well known for the New Year Rose Parade and the Rose Bowl. There is no doubt: It...
SUSS MicroTec Receives Order for Next-Gen Projection Scanner DSC300 Gen2
Garching, June 12, 2014 – SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and...
Wafer Level Packaging and Stacking take Center Stage at Asia Conferences
I thought I would go to Singapore, attend EPTC (Electronic Packaging Technology Conference 2013) and then take off on my... Rudolph Announces New Metrology Suite for Advanced Packaging
New NSX Metrology Series includes application-specific configurations to address unique metrology requirements for wafer level packaging, 2.5D and 3DIC Rudolph...
