Pasadena offers Roses and Technology

Pasadena offers Roses and Technology

California’s Pasadena is well known for the New Year Rose Parade and the Rose Bowl. There is no doubt: It takes commitment and organizational talent to make these events successful for 100+ years, and encourage every contributor to prepare and execute successful events every year.

Last week’s International Microelectronics Assembly and Packaging Solutions Conference (iMAPS) in Pasadena’s Convention Center, had a lot in common with above-mentioned events: Several of the fully committed 125 exhibiting technology companies can also boast 100+ successful years in business. Well organized and knowledgeable actors on stage and on the exhibition floor made this event very informative for the 957 conference attendees; a remarkable number for an IC packaging technology event. Read on for highlights of the sessions I attended.

Tuesday morning started with a keynote from TSMC’s Senior Director Doug Yu, with the compelling title: “Simpler is better!” He started by emphasizing the importance of “P3C2”, which stands for performance, power, profile, cycle time and cost. He then positioned TSMC’s high-performance chip-on-wafer-on-substrate (CoWoS), an interposer-based device, and its integrated fan-out (InFO), a low-cost fan-out wafer level packaging (FOWLP) technology, as examples of P3C2. Yu proudly mentioned that his team also developed the InFO package-on-package (PoP); currently the only multi-die packaging solution in really high-volume production. Everybody in the audience knew that he meant TSMC’s win in the iPhone 7. Since its launch last month, it’s shipping in very high volumes, and clearly takes advantage of the leading P3C2 benefits this packaging technology offers. Yu compared this package type with several others and emphasized that the InFO PoP is only 0.8mm thin and keeps the DRAM “comfortable” at 85°C, while the 16nm APU underneath rises up to 105°C junction temperature.

In the second keynote, Mark Brillhart, now CTO at Flextronics, talked about how his company is changing from an assembly house to a system design and manufacturing partner for customers. Just as he emphasized in his previous role at Cisco, Brillhart talked about how rapidly the Internet of Things (IoT) is growing and how important the role of MEMS and sensors is becoming. These devices capture events in the real world and feed them to local or remote compute centers for evaluation and to issue actionable commands. Multiple times in his speech, Brillhart emphasized the importance of reliability, and the growing need for software and standards for IoT. Last, but not least, he encouraged material suppliers to address the need for reliable new materials.

The third keynote, delivered by Reza Ghaffarian, Ph.D. from Jet Propulsion Laboratory (JPL), offered a very clever way of emphasizing the importance of reliability. During his 22 years in the services of NASA/JPL Ghaffarian contributed to many successful space programs and learned the hard way how a tiny component’s reliability problem can wreck a big and important mission. He shared many examples of both outcomes with us.

Session C, titled “Advanced Packaging and Enabling Technologies” was my focus for Tuesday afternoon.

Jan Vardaman from TechSerach International, Inc. outlined her forecast for the rapidly growing wafer-level packaging (WLP) technology and highlighted a very telling data point: The iPhone introduced in 2007 used 2 WLP solutions; the recently introduced iPhone 7 uses 38 WLPs to integrate lots of functionality into a very small space. In addition, this packaging technology offers very high performance per Watt. She also emphasized that chip-package codesign methodologies are very important for WLP to walk the fine line between costly over-design and risky/unreliable under-design.

Ennis Ogawa from Broadcom described some of the IC design challenges that the latest process technologies have in store for developers: High process variation, high power density, testability, reliability as well as considering the interactions between die(s) and packages.

Qualcomm’s Urmi Ray expressed very similar concerns and emphasized the need for accurate modeling of material characteristics. The coefficient of thermal expansion (CTE) mismatch, for example, causes major performance and reliability problems in the tightly packed WLPs. In addition to simulating chip/package interactions, she also highlighted the need for a chip-package-board design methodology. Considering wireless carriers and their suppliers plan to introduce 5G in the next few years, insertion loss (a.k.a. loss tangent) is another material parameter that needs to be characterized for up to almost 100 GHz.

Steffen Kroehnert stated that Nanium has shipped 700 million IC packages based on embedded wafer-level ball grid array (eWLB) technology, licensed from Infineon. Major applications Nanium  serves require optical element, MEMS, and antennas. Nanium offers up to 30×30 mm body sizes, with up to 6 RDLs. Kroehnert disclosed that packages with line/space of 8/8 microns are in qualification and 2/2 is in development. To avoid problems because of CTE mismatch, Nanium can offer materials with CTE from 2 to 60 ppm per degree Kelvin.

Dongkai Shangguan from StatsChipPAC, also an eWLB licensee, presented their broad product portfolio and the ongoing qualification efforts to expand it further. He reasoned about the cost benefits of panel-level processing and compared benefits and trade-offs of wire-bond packaging with flip-chip and FOWLP.

Tanja Braun from Fraunhofer IZM in Berlin introduced their development work for panel-level processing. He talked about mold-first versus chip-first flows for their 24 x 18-inch panels, allowing placement of about four times as many components as a 12-inch wafer. Braun invited the audience to join their development consortium starting in November of this year.

Wednesday started with a very educational keynote from Ron Huemoeller, Corporate VP at Amkor. First, he highlighted several key trends in our industry:

  • Company consolidations also among assembly houses
  • Focus on high-growth segments like mobility, IoT, and automotive
  • IC test increasing in complexity and importance
  • Large investments ($ 500 M/y) needed to keep up with IC packaging innovations.
  • “CPP” = Cost, performance and package profiles are the key differentiators for assembly and test houses (a.k.a. OSATs).

In the second half of his keynote, Huemoeller compared the “Big Five” packaging technologies: flip chip / WLCSP / MEMS / Laminate SiP / Wafer SiP. An excellent article describing benefits and trade-offs of the Big Five is here. Like speakers before and after him, Huemoeller also emphasized the need for chip/package codesign tools.

Wednesday’s second keynote was presented by Jon Greenwood, GM at Plexus in Idaho. His company offers US-based resources for integration of complex systems for military, medical, networking and industrial applications. He, like Flextronics’ Brillhart on Tuesday morning, pointed out that customers now expect much more than assembly and test services from their manufacturing partners today. Greenwood also highlighted the time-to-market advantage US-based engineering resources can offer their customers.

After the coffee break, I attended Session C again. Jerome Azemar from Yole Développement presented their perspective of the wafer-level market. Yole sees Infineon’s widely licensed eWLB technology as the most common wafer-level packaging solution today. Azemar projected that FOWLP packaging revenues will reach $2.5 B in 2021. Yole expects that it will take several more years for panel-level processing to mature. Azmar hinted that he expects Samsung will soon follow TSMC’s strategy and also offer chip and packaging solutions.

Chet Palesko from Savansys focused his presentation on a cost comparison between wafer-level versus panel-level processing. He not only talked about the major direct and indirect cost elements but also reasoned that the ecosystem for panel-level processing will require major investments. In contrast, for wafer-level processing, older, most likely fully depreciated wafer fab equipment, can be used. Palesko also mentioned that his cost analysis software and services are used for “pathfinding” to identify the most cost-effective IC implementation alternative.

StatsChipPAC’s Babak Jamshidi conveyed an encouraging view of the IoT market’s growth potential. Today’s seven to eight billion connected devices will grow to about 200 Billion by 2020. About half of these devices will use 4G or 5G for communication. Especially 5G – likely to be rolled out before 2020 – will shift a lot of the value creation from the die to the package. It demands very high-performance packages, as well as the integration of antennas in the IC package. StatsChipPAC can service both requirements with the eWLB technology. To learn more about the company’s application of eWLB and FOWLP in IoT and sensors, read this article published in the Meptec Report, which provides information on the 3D MEMS pressure sensors which we assembly using an eWLB-PoP method.

Aric Shorey from Corning’s Specialty Materials Division emphasized that glass has at least an order of magnitude less insertion loss (a.k.a. loss tangent) than silicon, an important feature for 5G applications. Corning can deliver glass in wafer and panel-form, in various thicknesses, even sandwich build-ups. Corning works with GeorgiaTech, the University of Florida and industry partners to broaden their portfolio and the use of glass for interposers and other IC packaging requirements.

The next conference iMAPS is organizing is the 13th 3D ASIP conference in Burlingame, near SFO. It will start on Tuesday, December 13 and conclude on Thursday, Dec 15. This 2.5/3D-IC focused conference will offer 3D- IC design, materials, manufacturing, and equipment information and demonstrate in many ways the benefits of packing multiple dies into on IC package in many ways. I look forward to meeting you there! ~ Herb