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Challenges in the Era of Semiconductor Miniaturization As process nodes continue to shrink, moving into the single-digit nanometer era, the challenges surrounding materials reliability and system performance are being redefined. With each new node, transistors become smaller enabling the integration of billions of transistors onto a single chip. However, this...
The semiconductor industry’s decades-long adherence to Moore’s Law doctrine of doubling transistor counts on monolithic devices every 18 – 24 months has been amazingly successful. It’s now possible to integrate tens of billions of transistors onto a monolithic die whose area may be hundreds of square millimeters. The resulting chips...
EVATEC AG, a leading supplier of thin film equipment and process solutions in Advanced Packaging, Semiconductor, Optoelectronics and Photonics applications, has successfully completed the installation of a Clusterline 600 Panel Level Packaging Etch system at Fraunhofer IZM, Berlin. The CLN600 platform is a dedicated Etch and Sputter equipment for FO-PLP...
I almost didn’t attend the keynote panel titled, Scaling the Walls of Sub 14nm Manufacturing, at SEMICON West last week, because in my experience as a blogger/journalist focused on advanced packaging, interposer integration and 3D ICs, discussions on scaling rarely talk about packaging. In fact, up until now, it’s been...
Stacking transistors on top of each other sequentially in the same front-end process flow is a concept that has been imagined to provide the semiconductor community with an alternative to the traditional scaling paradigm challenged by technical and cost roadblocks. LETI Advanced CMOS Laboratory introduced CoolCube™, a low-temperature process flow that provides...
With the continued innovations in packaging technologies and 2.5D interposers pushing 3D ICs further out from one end, and 16/14nm nodes already qualified without TSVs, making us wait until 10nm, are 3D ICs suddenly getting the squeeze from both sides? That’s one theory I took away from all the conversations...
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of...
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool...
Wouldn’t it be great to get a text notification that you are almost out of toilet paper at home rather than when it’s well… almost too late? Or how about an intra-nasal sensor that detects the level of acetone in your breath to tell you if you’re accumulating or burning...
2.5D Interposer: A configuration where dies are mounted side by side on one side of a thin (~ 100 um) silicon, glass, or organic interposer using through silicon vias (TSVs), through glass vias (TGV) or through substrate vias (TSV), respectively through the interposer to connect the dies with the package...
