Matches for your search: "fan-out wafer level packaging "
The month of September saw continued momentum in the semiconductor industry, highlighted by exciting industry events, innovative technology launches, and international collaborations. Companies unveiled new process solutions, inspection systems, and AI-enabled design tools, emphasizing advancements in materials, memory, and compound semiconductor manufacturing. Workforce development initiatives strengthened ties between academia and...
Riding the 3D/Heterogeneous Integration Wave For decades, the ability to achieve the necessary power, performance, area, and cost (PPAC) in semiconductor manufacturing had been largely driven by 2D design rule shrinks enabled through advances in lithography. In recent years, however, the rising costs and complexity associated with 2D shrinks have...
The impressive industry grouping of ASE, AMD, ARM, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC in early March announced the formation of an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. Those of you who follow IFTLE know this is exactly what...
Reno Sub-Systems (Reno), a developer of high performance radio frequency (RF) matching networks for leading-edge nanoscale semiconductor manufacturing, today introduced its new GenMatch™ Series that integrates the company’s proven solid-state Electronic Variable Capacitor (EVC™) RF match and Precis™ generator technologies into a single unit. The systems have a footprint similar...
The business model in today’s competitive world of commerce has shifted over recent years to “services.” Companies like Microsoft, Amazon, and Google are prime success stories that have advanced the industry with business-enabling services. These economic productivity improvement services allow their customers to focus on product architecture, design, and quick...
Eight years in the making, the IEEE Std 1838™-2019 Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits — or IEEE 1838, DfT for 3D IC, as it’s known in inner circles – was published on March 13, 2020. Simply put, this standard will allow stacked dies in 3D ICs to connect...
SEMI held its annual Industry Strategy Symposium (ISS 2019) at the Ritz Carlton in Halfmoon Bay, CA January 6-9, 2019. Many high-level executives represented key areas of the electronic products supply chain. Former government officials emphasized that our country’s leaders recognize the strategic importance of semiconductors. The theme of ISS...
When is an active die not an active die? When it’s an active interposer, of course! Ever since Nicolas Sillon, former head of CEA Leti’s 3D Integration program, first talked about the research institutes’ work with interposer technology for 3D integration, the term “active interposer” has sparked controversy and begged for definition....
There’s probably no more fitting venue for discussing future directions for processing and packaging technology in integrated circuit fabrication than the Computer History Museum in Mountain View, CA. After all, “The mission of the Computer History Museum is to preserve and present for posterity the artifacts and stories of the...
Semiconductor supply chain, ecosystem, value chain: whatever you call it, its become a hot topic of discussion, and one that is near and dear to my heart as a supporter of 3D IC commercialization. Well over a year (maybe even going on two) we’ve been hearing suggested changes like a...
