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In the rapidly evolving microelectronics landscape, demands for higher performance, reduced size, and faster development cycles are driving the industry toward more innovative design paradigms. This was traditionally accomplished by miniaturizing transistors within microprocessors as was described by Moore’s Law. Gordon Moore of Intel estimated that the number of transistors...
Live from “Silicon Desert”: The news is all about huge spending by TSMC and Intel. Investment in advanced packaging (2.3/2.5/3D including chiplets) is increasing. As a 5nm design effort tops $500M and photo tools approach $150M, it was necessary to bust up systems-on-chip (SoCs) into re-partitioned systems – where functions...
In order to remain competitive in the Internet-of-Things (IoT) environment, medium-sized industrial and process measurement technology companies must increasingly integrate their sensor circuits on ASICs (Application Specific Integrated Circuits). The semiconductor industry is currently meeting this need with lower costs for development processes and lower thresholds in terms of production...
Once a month, MEPTEC, now managed by Ira Feldman, organizes a very informative luncheon at SEMI in Milpitas. On November 13, 2019, two well-known industry experts, Anand Joshi and Tom Dillinger, addressed today’s hot topics —neural networks and System-on-Chip (SoC) design challenges — with short, but very informative presentations. Can...
This year’s IMAPS International Symposium purported to have “the most interposer and 3D content under one roof.” I’m not sure about that, but there was certainly enough 3D going on at IMAPS 2014 to spark my interest. Here are some highlights I came away with, based on presentations, interviews with...
Because I interact with people involved in 3D across the entire spectrum of its meaning, I tend to be privy to varied perspectives and opinions when it comes to the adoption of TSV as a method of interconnect for 3D integration. One thing is perfectly clear – support for TSV...
While it was Good Friday for most, it was 3D Friday for those of us who attended the 19th Annual Electronic Design Process Symposium (EDPS), held last week in Monterey CA. What an amazing location! For an ocean-starved desert dweller like me, it was hard to tear my eyes off...
I just finished putting together a presentation for the upcoming BiTS Workshop March 7-10, 2010 taking place in my backyard in Mesa, AZ.
The SMTA and Chip Scale Review magazine are pleased to announce five half-day tutorials for the 6th Annual International Wafer-Level Packaging Conference, held October 27-30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, California.
The IWLPC tutorials are application oriented and structured to combine field experience with...
As I was unable to attend Design Automation Test in Europe (DATE 2009) myself, but felt the information being shared there would be useful to my readers, I asked fellow 3D enthusiast, Yann Guillou, new technology marketing, St Ericsson, if he would write a guest post for “Françoise in 3D”....
