Because I interact with people involved in 3D across the entire spectrum of its meaning, I tend to be privy to varied perspectives and opinions when it comes to the adoption of TSV as a method of interconnect for 3D integration. One thing is perfectly clear – support for TSV varies depending on a person’s position in the industry.
For obvious reasons, the strongest supporters are those whose livelihood depends upon the adoption of TSV and those most strongly opposed depend on it being relegated to niche applications only. The rest of the pack falls somewhere in between, and it’s perhaps those individuals who can offer the most objective perspectives of the future of TSV and its likelihood for market adoption for high-volume applications.
The anti-TSV camp is populated with those who are focused on developing low-cost alternative approaches to interconnect that leverage the existing infrastructure which undoubtedly leads to faster time-to-market. Even the pro-TSV camp is willing to admit that as long these alternatives can get the job done at either the package or bond-pad level (wire-bond, Vertical Circuits’ VIP process, 3D Plus’ wDoD, Amkor’s TMV PoP, and Tessera’s µPILR PoP all come to mind) there’s no real reason to adopt TSV, UNLESS ultra-low cost processes can be developed.
What’s important to remember is that when people claim that these technologies will hold up the market adoption of TSV, they’re only partly right. In reality, it may hold up market adoption for those applications better served by traditional interconnects, like stacking flash memory.
But at a certain point, TSV will be the solution; thus the push by TSV activists to educate the benefits of the next level of 3D integration and define it as THE 3D technology. I’m referring to the ultimate 3D achievement of heterogeneous device stacking at the circuit level. According to most experts, TSV is the ONLY way to cost effectively reap the benefits of increased speed and density for higher performance at lower power and cost offered by repartitioning CMOS layers. As roadmaps for this ultimate 3D IC don’t predict volume production of these for another 8-10 years, current alternatives really aren’t holding that up.
This is why many refer to 3D integration as an evolutionary process. One thing invariably leads to another, and we learn something useful along the way. Feasibility of each step in 3D integration does more than bring a new technology to market, it actually opens the path to the next level of innovation and development. It’s the reason IMEC invests in all 3D technologies; they know it’s a means to an end. Skipping over any of these steps would not make things happen any faster. Each integration scheme will find its place in the value chain. And at some point, decisions will be made to reduce the available approaches to a select few and standardize them. This is what will lead to volume production.
Fortunately for me, my livelihood depends on 3D configurations of as many sorts as possible taking over the semiconductor world, so I am gloriously free to support everybody’s technology advancements, and don’t have to take sides (thus the strategic naming of this website as 3D InCites rather than TSV InCites!) I’ll leave that up to you. What’s you’re opinion on TSVs as a 3D interconnect solution? — F.v.T
