Show Me The Money: 3D Friday at EDPS

While it was Good Friday for most, it was 3D Friday for those of us who attended the 19th Annual Electronic Design Process Symposium (EDPS), held last week in Monterey CA. What an amazing location! For an ocean-starved desert dweller like me, it was hard to tear my eyes off the waves and pay attention at what was going on in the front of the room… but I managed and it was definitely worth tuning in to.

Organized by Herb Reiter, of eda2asic (fellow 3D enthusiast and the now-official King of 3D) on behalf of the EDA Working Group, this event was refreshing change from a focus on engineering to a real get-down-to-business agenda orchestrated to engage customers and EDA vendors in a dialogue about the expectations moving forward with regard to 3D IC adoption.

Keynote speaker, Riko Radojcic (Mr. 3D) of Qualcomm and Arif Rahman of Altera each set the tone for discussion by talking about the advantages of 3D IC from their company’s perspectives. Qualcomm’s focus is memory on logic. “Why 3D?” asks Radojcic. “Because 2D is getting awfully complicated. Wide I/O memory is a very good thing. The only way to do it is with some kind of 3D stacking, traditional wirebond doesn’t have the density. 3D gives us the ablitly to turbo-charge transistor levels. System integration level is going up, form factor is going down, and this seems like a good thing.”  

Rahman talked about 3D for FPGA, noting that FPGA platforms are ideally suited to silicon convergence. Altera’s 3D vision is one of heterogenous system-in-package integration that will mix-and-match silicon IP and features an integrated design flow and system test methodology; and will maximize system performance and power in the smallest form factor at a reduced system cost. “We see 3D as an enabler to incorporate system-level capabilities.” noted Rahman. “Die stacking provides unique business opportunities to move up the value chain with improved time to market and product differentiation.”

Radojcic outlined an EDA ecosystem with three “buckets” labeled Design Authoring, Pathfinding, and TechTuning to address three key challenges: actual chip design, design/technology and concept exploration, and physical space exploration, respectively. Leveraging 3D will be all about managing choices, he noted. “The winning 3D product will be architected specifically to leverage 3D technology. The selection of choices is product specific.” Said Radojcic, “You can’t do it on a spreadsheet. You need spatial awareness.” He added that 3D design tools require heterogeneity to address multiple stacking styles and orientations, multiple tech files, multiple levels of hierarchy, and multiple resource constraints. He talked about the importance of considering material properties, stress management, and thermal issues as part of the design process. And for each 3D configuration; memory on logic, interposers, and logic on logic, he described the current design environment, listing the elements that exist, are ‘in flight’ and ‘like to have’.  

The design ecosystem of the future, according to Radojcic will be highly integrated and focus on the complete system. He used the prefix, “multi” a lot, as in multi-technology (heterogeneous integration), multi-dimensional (3D on-chip and stacking) , multi-physics (electrical, thermal, mechanical) and multi-disciplinary (die/package/system). But, this cannot be done all in a single tool or even a single flow. “We need a way to intelligently partition the problem and maintain benefits of integration. At least one element of the eco-system must view the entire system.  Lets call it ‘PathFinding’ or something that does quick ‘n’ dirty design exploration,” said Radojcic. “Additionally, we need a way to intelligently incorporate thermal and mechanical considerations that can be imported into at least one level of design abstraction as separate design constraints.  Let’s call it “TechTuning’…. or something that does thermal/stress design exploration.”

From Altera’s perspective, Rahman said “What we’re doing today is hacking existing tools, adding wrappers, etc. What we’d really like to see is 3D enable tools from the get go.”  He identified a significant number of gaps in the desired EDA flow for 3D integration. For example, in pathfinding for early assessment, he said that existing RTL-to-GDS and die/package co-design flows are too cumbersome for quick and cross-functional “what if” analysis. With regard to physical design verification, there are gaps that inhibit the ability to manage data base size and process shrinks. They’ve had to resort to custom ad-hoc methods invented on the fly for tier-to-tier DRC/LVS. This poses a challenge with multi-vendor or mixed technology integration. There were more gap examples, but the overall message was this: EDA tools need to evolve to support higher-level system integration enabled by die-stacking.

Show Me the Money
Without actually saying the words, the implication from both these presenters was that the solutions needed to come at the lowest price possible. (Now that I think about it, Radojcic did actually say the word “cheap” here and there.) This sparked some indignation around the room that became the topic of lunch discussion, as well as during the afternoon panel. Because the bottom line is, this extensive wish list does not come cheap. Vendors say they have invested considerable funds in R&D towards developing these tools for their customers, and have yet to see a return on investment. Unlike process development, where costs are shared by the manufacturers and suppliers (equipment and material) the cost of EDA tool development rests firmly on the shoulders of the tool vendor, and the ROI does not come until the customer purchases the tool. According to Samta Bansal, product marketing manager at Cadence, who leads the company’s 3D-IC efforts (aka the Princess of 3D), this is becoming a real sticking point.

Cadence has clearly been leading the charge among the big 3 vendors (Cadence, Synopsys and Mentor Graphics) with regard to 3D IC EDA tool development. Bansal reports that over the past 5 years, Cadence has invested 14-20 man years($7-10M) in R&D development and test chip support for 3D integration at customers’ request, with little or no return on investment thus far.  Because of this, she’s feeling pressure from both management and R&D. In response to the needs outlined by Rahman and Radojcic, she said “We would  LOVE to provide all of these things for you. Just show us the money!”  In other words, buy our tools to develop your 3D devices.  Phil Marcoux, of PPM Associates concurred. “It amazes me how we all dance around the cost issue. We need to take a realistic view of the value proposition while Xilinx is laughing all the way to the bank.” he said. Or as Herb Reiter noted, “There’s no such thing as a free lunch!”

So while the customer list of needs appears to be rather daunting, the vendor list is short. What they need are sufficient resources to get the job done. So come on folks, show them the money! ~ F.v.T.

P.S. It was a very full day. Look for more coverage later this week.