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Indium Corporation Senior Area Technical Manager for East China, Leo Hu, is scheduled to deliver a presentation on low-temperature solder material in semiconductor packaging applications at SiP China Conference 2024 on November 27 in Suzhou, China. The presentation, titled Low-Temperature Material Discovery and Readiness for First-Level Interconnect in Semiconductor Packaging, will explore the latest advancements...
Achieve higher integration density with collective die-to-wafer bonding Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes...
Onto’s JetStep® lithography and Firefly® G3 inspection systems offer a powerful solution as the industry pursues glass core panel transition Wilmington, Mass., July 9, 2024 – Onto Innovation Inc. (NYSE: ONTO) today announced Onto Innovation’s glass substrate suite featuring the JetStep® X500 panel-level packaging lithography system with hybrid substrate handling...
While most of us in advanced packaging is familiar with CEA-Leti, CEA-List ( Laboratoire d’Intégration de Systèmes et des technologies) is one of three specialized technological research institutes of CEA specializing in digital systems. Denis Dutoit, of CEA-List, presentation on “Chiplet Partitioning Can Balance Among Performance, Flexibility and Scalability” at...
Until recently, many companies considered diversity a “nice to have.” Companies supported diversity and inclusion because they wanted to be good citizens because it was the right thing to do, and – for some, cynically – because it was good PR. But now research is proving the business case for...
Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing...
At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to...
As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti...
At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle...
Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way...
