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Artificial intelligence and machine learning (AI/ML) can have various applications in smart manufacturing for semiconductor fab, advanced packaging, and electronics manufacturing, and it typically involves several key elements: sensing, connectivity, predicting, and control. As recognized by many industry organizations, smart manufacturing matures through several levels: reactive, preventive, predictive, and autonomous...
SUSS MicroTec, leading supplier of equipment and process solutions for the semiconductor industry, announced today a far-reaching collaboration agreement with BRIDG, a not-for-profit, public-private partnership focused on production process technologies, advanced system integration, and 200mm microelectronics fabrication advancing next-generation nanoscale technology. This partnership puts an unprecedented array of SUSS MicroTec...
The Electronic Design Process Symposium – EDPS 2919 – is known in the IC design community as a rather small (50 – 100 participants), but a highly interactive workshop. The 26th edition, hosted again this year by SEMI at its Milpitas headquarters, October 3 -4, 2109 featured both EDPS IC design...
SEMICON West and the Electronic System (ES) Design West were, for the first time, co-located at the Moscone Center in San Francisco, from July 9 to 11, 2019. In addition to most keynotes, I reported about here, This blog talks about some in-depth technical presentations on test and the progress...
EV Group (EVG) today unveiled its maskless exposure technology (MLE™), a revolutionary next-generation lithography technology developed to address future back-end lithography needs for advanced packaging, MEMS, biomedical and high-density printed circuit board (PCB) applications. The world’s first highly scalable maskless lithography technology for high-volume manufacturing (HVM), MLE combines high-resolution patterning...
Wafer and panel-level packaging (WLP/PLP) offers technical and business advantages, compared to traditional IC packages. These cost-effective packaging solutions attracted more than 800 industry experts to the International Wafer Level Packaging Conference (IWLPC 2018) in San Jose’s DoubleTree Hotel at the end of October. In case you were wondering, a...
The message remains consistent: following Moore’s Law is no longer economical for most IC designs. A major part of the IC value creation is moving from the die to the IC package. Now advanced packaging technologies and materials enable combining multiple dies with heterogeneous functions as well as high-quality passives...
From the keynotes to the sessions to casual conversation, automotive electronics was a hot topic of discussion at SEMICON Europa 2017. That’s likely because Europe leads the world in automotive OEMs and is home to four of the top 10 semiconductor providers in the automotive industry. With over 22% growth...
Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would...
When I saw that Dev Gupta, Ph.D, of Advanced Packaging & Systems Technology Laboratories, LLC (APSTL) was presenting at the IMAPS Arizona Chapter luncheon last week, there was no questioning my attendance. Dr. Gupta has been an active participant on 3D InCites, offering regular commentary on posts, so I was...
