When I saw that Dev Gupta, Ph.D, of Advanced Packaging & Systems Technology Laboratories, LLC (APSTL) was presenting at the IMAPS Arizona Chapter luncheon last week, there was no questioning my attendance. Dr. Gupta has been an active participant on 3D InCites, offering regular commentary on posts, so I was particularly eager to hear and report on what he had to say on his chosen topic of the discussion: Package Level Integration – Roadmap Based on Performance Modeling.
APSTL’s core competency is performing in-depth analyses of package materials and processes, package failure and root cause analysis; and package qualification and supplier evaluation per established industry standards. As such, Dr. Gupta has spent considerable time analyzing the pros and cons of 2.5D and 3D TSV technologies, as well as developing theoretical alternative approaches to TSVs. Dr. Gupta’s presentation focused mostly on the former, and touched briefly on the latter with an example of the benefits of APSTL’s SuperPoP package. I was looking forward in particular to hearing more about the SuperPoP, as I heard Dr. Gupta presentation on this topic last year at IMAPS DPC 2013.
In his talk, Dr. Gupta reiterated the well-known difficulty in keeping up with Moore’s Law due to increased cost and technology complications (lithography, transistor structures, etc.) of scaling to further nodes, and how this is driving integration at the packaging level. Furthermore, at the chip level, design related issues of how to pack more SRAM on an SOC are making it more difficult to shrink the die. His take is that whatever solutions we come up with, they have to be low risk, affordable, and not have performance degradation.
Classifying current solutions devised by the packaging community as evolutionary (SnAg capped Cu micropillars, WLP, and shrinking substrate geometries); revolutionary (3D ICs with TSVs, 2.5D interposer); and intermediate (modifications to PoP package ie: Invensas’ BVA technology and APSTL’s SuperPop); Dr. Gupta clearly favors the intermediate approach. Although he acknowledged that the SuperPop cannot achieve the high density levels of 3D ICs with TSVs, it’s his opinion that the industry will not require that level of density for “quite a long time.”
Here’s what he shared about the SuperPoP: Based on modeling done by APSTL, if a baseline PoP package (such as currently used to integrate SoC and LP DDR memory in a 3D stack) is modified by inserting a “Magic Chip” in the interconnect between (chip and package), then the bandwidth can be doubled to 12.8 GBps, and the power dissipation in interconnect halved without any increase in package external dimension. According to Dr. Gupta, initial build and tests have been encouraging. These have involved inserting a simpler version of the “Magic Chip” into an older SoC and LP DDR memory in a PoP package. The power consumption in running benchmark programs was reduced by 7 to 10%, implying a saving of power consumption in just the SoC/Memory combination in a SmartPhone by nearly 30%. Gupta claims insertion of “Magic Chips” into high-bandwidth 2D modules as used in servers can be expected to produce similar improvements.
Dr. Gupta acknowledging the many advantages of TSVs, noting that it offers 4x the I/O density of flip chip technologies, allows for more parallel data transfer, provides a shorter interconnect between chips, and reduces parasitics by as much as 90% for a given bandwidth, which corresponds to a reduction on power dissipation. However he sees the challenges of stress and thermal effects of the TSV stacks; using Cu as the fill material when there are clearly CTE mismatch issues with Si as well as Cu pumping issues; and a process flow that is “in flux” as reasons to go in another direction. He is very concerned about putting TSVs in active areas, noting, “It’s like performing a root canal on a finished tooth,” which is why he sees 2.5D interposers as a good “interim solution.”
While many companies have announced 3D DRAM on logic products in the works, (Samsung’s 3D DRAM; Texas Instruments memory stack on processor; JEDEC’s first stab at Wide I/O DRAM) Gupta pointed out that “nothing has come out of it,” despite the fact that Micron is sampling its Hybrid Memory Cube and says it will begin production in 2014. And indeed, he said that Samsung has gone in a different direction altogether with its recent commercialization of 3D VNAND, which is based on a monolithic 3D approach. He cited Tezzaron Semiconductor as “the only company that has worked through all of the issues and has something in production.” But Tezzaron has taken “a radically different approach” by using tungsten instead of copper as a via fill, and stacking layers of circuitry to create a memory stack and thinning after, rather than stacking two wafers and having to rely on temporary bond/debond to perform the backside processing steps.
Dr. Gupta’s main point was this: “Totally new and disruptive processes should be developed with complete evaluation using test chips,” he said. “Premature optimization of individual process steps may cause delays.” In his opinion, the fragmentation of the industry has caused us to miss the big picture with 3D TSVs, and this is why it’s taking so long to get commercialization.
He says when we’re dealing with high performance packaging, we must evaluate performance before getting involved in mechanical details. “Theoretical analysis can open new opportunities like SuperPop,” he noted, stressing that the industry needs “a lot more modeling.” This is the approach he says his company has taken with developing the SuperPoP, and he believes the device can meet the current performance requirements and is a suitable intermediate solution as an alternative to TSVs in the near term.
As APSTL’s business is based first in theoretical analysis, they are not in the business of manufacturing parts; therefore SuperPoP is not yet in production, Dr. Gupta explained. He also The intention with the SuperPoP is to follow a license business model. He is currently seeking manufactures interested in licensing the SuperPoP to take it into commercialization. The question is, do you believe in Magic? ~ F.v.T.
PS: If you are interested in learning more, Dr. Gupta is teaching a professional development course titled Package Level Integration – 2-D, 2.5-D and 3-D: Impact on Handheld Systems. Monday March 10, 2014, at the IMAPS Device Packaging Conference in Fountain Hills AZ.