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Glass Core vs. RDL Interposer Substrates: Ready for Prime-Time?

Special Session at the 75th Annual IEEE Electronic Components and Technology Conference (ECTC) Explored Their Relative Merits As the traditional scaling of transistors forecast by Moore’s Law has become more difficult and costly, the new frontier for semiconductor development is to find ways to combine different types of chips into...

design-for-test

Affordable and Comprehensive Design-for-Test of 3D Stacking Die Devices

The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore’s law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing. Developers of high-end...

Workforce Development Considerations in the Megachips Era

A recent Wall Street Journal article, The Microchip Era Is Giving Way to the Megachip Age, explains how the chip industry is transitioning from monolithically integrated chips to stacking chiplets to make megachips. In the U.S., DARPA is embarking on the Next Generation Microelectronic Manufacturing initiative focused on three-dimensional heterogeneous...

Semiconductor Companies Participate in the 4th China International Import Expo

The 4th CIIE was held successfully, let’s see which semiconductor companies appeared at the event. The opening ceremony of the 4th China International Import Expo (CIIE) and Hongqiao International Economic Forum was held in Shanghai on November 4th, 2021. Nearly 3000 exhibitors from 127 countries and regions appeared, and the...

Samsung VP to Keynote IWLPC

San Jose, California – USA – The International Wafer-Level Packaging Conference and Expo announces Dan Oh, Ph.D., Engineering VP of the Test & System Package (TSP) unit at Samsung Electronics will deliver the opening keynote presentation of the virtual event.  The presentation, “Trends, Challenges, Opportunities in Advanced Packaging for Smart...

Diversity, Parity, Prosperity: Perspective of an Industry Veteran

“Don’t surround yourself with yourself …” Yes, from I’ve Seen All Good People. “At Japan’s Most Elite University, Just 1 in 5 Students Is a Woman.” The New York Times, 08 December 2019 “The semiconductor industry isn’t known as a standout example of diversity and inclusion. But that’s changing.” Jane...

IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration

Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial intelligence (AI) and high-performance computing (HPC). They also report a need for new electronic design automation (EDA) solutions because the traditional design doesn’t fully address the latest power and signal...

How to Transform Innovative Technologies Into Customer-Specific Solutions

Technology innovations don’t reach customers right away. Since 1980 I have observed how our industry has improved key parameters like cost per function, power dissipation, form-factor, complexity and clock-speed by many orders of magnitude. However, every new technology took at least several years, sometimes more than a decade, until it...

Is the IoT Headed for the Trough of Disillusionment?

No SEMI Summit would be complete without a lively panel discussion that puts industry experts in the hot seat. The panel at the first SEMI European MEMS Summit, titled IoT Beyond the Hype: What are the Hard Facts?, didn’t disappoint for much as what was discussed, as for what was glossed...

PDN Design, Target Impedance and Path Finding for IC, Package, and PCB

I am fortunate to work with Prof. Madhavan Swaminathan, Founder, CTO, E-System Design, and inventor of our algorithms. Long ago, as an undergraduate engineering student at University of Illinois focused on integrated circuit (IC) design, I enrolled in the required ElectroMagnetics (EM) course to discover it was all about large...