Francoise News - Page 26
Silicon Saxony: Leading the Charge in More than Moore
Since the days even before the reunification of Germany; Saxony, and particularly Dresden, has been a vital center for microelectronics development...
Fogale Nanotech: Building The Swiss Army Knife of 3D IC Metrology and Inspection
In the world of 3D ICs, where features are becoming finer and submicron accuracy and precision is more important than...
Nimes, France: Influencing 3D Architectures for 2000 Years
I first visited Nimes, France when I was sixteen, on one of those whirlwind, ten-day, school-organized trips with my French...
A Solder Bump Expert’s Take on the Expanding World of Advanced Packaging
An interesting take-away from the keynote talk delivered by Brandon Prior, Prismark Partners, at this year’s IMAPS International Device Packaging...
Latest Developments in Cleans for TSVs and Cu Bumps
At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on...
Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel
All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt,...
3D InCites Partners with SEMI and TechSearch International for the 2014 3D InCites Awards Program
Proceeds to Benefit STEM-based Scholarship Programs PHOENIX– March 18, 2014 – 3D InCites, the premier online content source for reliable...
Is the Road to 3D ICs Paved with 3D SOC?
Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its...
Interconnectology Revisited: Pizza Anyone?
Interconnectology returned as a topic of discussion to the 2014 BiTS Workshop through a keynote discussion delivered by Invensas’ president,...
Making Progress with 3D IC Design and Test
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D...
Magic Chip-powered SuperPoP offers Near-term Alternative to TSVs
When I saw that Dev Gupta, Ph.D, of Advanced Packaging & Systems Technology Laboratories, LLC (APSTL) was presenting at the... Dynaloy™ Researchers to Detail One-Step Cleaning Process for TSVs
INDIANAPOLIS, Ind., February 24, 2014 – A team of researchers from Dynaloy and Solid State Equipment Corporation (SSEC) have developed...
TCI for Wireless Chip Stacking; Progress for Monolithic 3D
Every once in a while, it’s important to remember that through silicon vias (TSVs) might not be the only game...
Progress Reports for 3D IC Thermal Management and Test
In Jan Vardaman’s recent readiness report card issued at 3D ASIP in December, 3D IC thermal management issues scored and...
Fraunhofer EMFT: 25 years of 3D Integration in Munich
Wouldn’t it be great to get a text notification that you are almost out of toilet paper at home rather...
Triple I Prevails at EV Group
Invent, Innovate, Implement continues to be the mantra at EV Group, supplier of wafer bonding and lithography equipment for the MEMS,...
The 411 on CEA Leti’s Interposer Roadmap
When is an active die not an active die? When it’s an active interposer, of course! Ever since Nicolas Sillon,...
2.5D and 3D IC Technologies: Application Ready but Cost Limited?
Two schools of thought clearly emerged at last week’s European 3D TSV Summit, which took place on January 20 and...
