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Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. Lujan did a very good analysis on the cost comparison of fan-out wafer-level packaging (FOWLP)  with chip-first and die...

Temporary Bonding and Debonding Technologies for Fan-out Wafer-Level Packaging

Fan-out wafer-level packaging (FOWLP) is a cost-effective way to achieve high interconnect density and to manage larger I/O counts within an affordable package. It enables smaller footprints, higher interconnect density, better routing and thinner packages than current technologies. [1] A standard FOWLP wafer comprises known good die (KGD) and a...

Warpage Issues in Fan-Out Wafer Level Packaging

As you all know, warpage is a critical issue for fan-out wafer/panel level packaging. Many people like to talk about it, however, most of them don’t know what they are talking about. Let’s use the chips first, face-up fan-out wafer level packaging (FOWLP) approach as an example. Also, let’s consider three redistribution...

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer...

A Fan-Out Wafer Level Packaging Epiphany

I’ve had an epiphany regarding fan-out wafer level packaging (FOWLP). Epiphany: “A usually sudden manifestation or perception of the essential nature or meaning of something.” In FvT’s piece “Spotlight on FOWLP, Monolithic 3D IC, and 3D TSVs,” (13 May 2015) I am quoted saying: “Show me where monolithic or FOWLP...

Chasing the Fan-out Wafer Level Packaging Rabbit at IWLPC 2015

Sadly, this year it was the 3D session track that had lots of empty seats at the 2015 International Wafer Level Packaging Conference (IWLPC 2015), which was a bit surprising since 3D is really hitting its stride with so many products in high performance computing on the market. Next door,...