Amkor Technology, Inc. is one of the world’s largest providers of outsourced semiconductor packaging and test services. Founded in 1968, Amkor pioneered the outsourcing of IC packaging and test and is now a strategic manufacturing partner for the world’s leading semiconductor companies, foundries and electronics OEMs. Amkor’s operational base includes production facilities, product development centers and sales and support offices located in key electronics manufacturing regions in Asia, Europe and the USA.

Advanced CFD/FEA simulators are great if you have the time to build up a detailed 3D model but often you need a quick and accurate answer to a heat transfer question and you just can’t wait around for fully calibrated model. Advanced CFD/FEA solvers with steep learning curves don’t make it easy to build up a model based on your intuition because you have to be good at 3D drawing, understand how all the boundary conditions should be set, and setup many control parameters for any simulation you will run before you get to a reasonable answer. Use Anemoi Thermal Solver to easily create a model today that gets you to a solution to thermal problems quickly.

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.

 

Deca was born of a passion to transform the way the world builds advanced electronic devices. In our first decade, our 10X thinking brought to life exciting breakthroughs for leading mobile semiconductor companies. From initial applications in traditional semiconductor packaging, to the growth of chiplets and heterogeneous integration, we have created key foundational building blocks for the future. Our world class investors, including Infineon, Qualcomm, ASE, nepes and SunPower, are respected industry leaders who provide us with the strength and visibility to create an entirely new model.

 

Our passion for science and technology is what drives our 62,770 employees in 66 countries to find solutions to some of today’s toughest challenges and create more sustainable ways to live. We are here for people at every step, helping to create, im-prove and prolong life. We deliver personalized treatments for serious diseases and enable people to achieve their dream of becoming parents. We empower the scientific community. Our tools, services and digital platform make research simpler, more exact, and help to deliver breakthroughs more quickly. Our solutions accelerate access to health by assuring tests are accurate and the medicine we take can be trusted. We are the company behind the companies, advancing digital living. Our science sits inside technologies that are changing the way we access, store, process, and display information. Our innovations are unlocking the power and potential of data to open new possibilities to transform life on Earth as we know it

 

Mosaic Microsystems is a microelectronics and photonics packaging company focused on glass and other thin substrates as a platform material. We provide integration products and services for a range of microelectronics applications, photonics, RF/mmWave, MEMS and sensor technologies. Learn more about the industries we serve here. Mosaic has offices and clean room space at 1999 Lake Avenue and is headquartered at 500 Lee Road in Rochester, NY.

 

 

Siemens EDA – The pace of innovation in electronics is constantly accelerating. To enable customers to deliver life changing innovations faster and become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services.

 

 

 

Special Presentation #3

3DIncites – Dean Freeman

Supporting the Chiplet Integration Ecosytem

Thursday, January 26, 2023 10:40-10:50

 

Conference Tracks

Tuesday, January 24th
08:30-Noon
Pre-Conference Tutorial C: Advanced Packaging Methods (Pre-Conference Tutorials Track)
Moderator: Adam Cron, Distinguished Architect, Synopsys

Organizer: Lihong Cao, Director Engineering, ASE Group

Speaker(s):
Session Description:
The days of simply selecting a chip package from a few common alternatives are over. Designers using chiplets must integrate package design with chip design and integration. They must have tools that consider packaging throughout the design process, so they can optimize cost, throughput, and heat and power factors over all stages. The goal is a one-stop shop providing heterogeneous integration that will drive faster time-to-market. Packaging can be a major way to add value to the ultimate product and meet the needs of system-level users.
Tuesday, January 24th
01:00-5:00 PM
Pre-Conference Tutorial E: Design Methods (Pre-Conference Tutorials Track)
Moderator: Bill Gervasi, Principal Systems Architect, Nantero

Organizer: Tony Mastroianni, Advanced Packaging Solutions Director, Siemens EDA

Speaker(s):
Session Description:
Designing a chiplet is much like any other IC design, since the designer must balance among the usual power, performance, and area (PPA). However, new issues come into play since the chiplet must fit into the overall chip design, so the designer must focus on interfaces and system-level issues. The interfaces must offer high bandwidth without using much chip area or power. Furthermore, the designer must make the chiplet be a useful citizen. It should serve a general purpose that will allow it to fit into a range of designs and interface neatly with all of them. As chiplets become commonplace, many people will design them for sale or inclusion in libraries.
Tuesday, January 24th
01:00-5:00 PM
Pre-Conference Tutorial F: Power and Thermal (Pre-Conference Tutorials Track)
Moderator: Sonia Leon, Sr Principal Engineer, Intel

Organizer: Andras Vass-Varnai, Portfolio Development Executive, Siemens EDA

Speaker(s):
Session Description:
Power and thermals are critical design criteria for chiplets. They must be low enough to allow for use in many applications and in repeated inclusions in designs that need more instances to achieve scalability and performance criteria. Tools are also needed to do power and thermal analyses globally as part of heterogeneous integration. Such analyses must include the interfaces between chiplets as well as the chiplets themselves and interactions among them. Designers must be aware that thermal constraints may limit operating frequencies and usage levels of cores and other facilities.
Tuesday, January 24th
05:00-6:00 PM
Superpanel: Successful Co-Package Design in a Post-Moore Era (Panel Track)
Moderator: Jan Vardaman, President, TechSearch International
Panel Members:
Panelist: Paul Franzon, Professor, North Carolina State University

Panelist: John Ferguson, Director Product Management, Siemens EDA

Panelist: Brett Wilkerson, Product Development Engineer, AMD

Panelist: Bob Patti, CEO, nHanced Semiconductors

Session Description:
The next design node is already seeing wide use of chiplets with all major chip makers adopting them. Is this break-it-apart and put-it-back-together approach a winner? Will we reduce design time and cost or are we moving the effort into the new integration stage? Do some heterogeneous integration methods work much better than others? How do designers find the best options for their applications? Will test costs explode or can we control them with a design-for-test strategy? Where does hybrid bonding fit into the design and what are the limitations? Are co-design and co-optimization the keys to the kingdom? How do we define a strategy that will lead to success in the post Moore’s Law world?
Wednesday, January 25th
02:00-3:00 PM
A-101: Packaging – 1 (Design/Packaging/Interfaces/Applications Track)
Moderator: Junho Choy, Engineer, Siemens EDA
Paper Presenters:
Improving Electromagnetic Simulation for Chiplet-Based IC Designs
Feng Ling, President, Xpeedic

Handling Thermo-Mechanical Stress in Chiplets
John Wilson, Business Development Mgr, Siemens EDA

Improving Device Fabrication with Thin Glass Interposers
David Levy, Sr Scientist, Mosaic Microsystems

Session Description:
Packaging has become a major stage in chiplet-based design. It greatly affects both power analysis and the introduction of bases (such as interposers) for interconnections, power, clocking, and other system requirements. Interposers provide a good base on which to build chiplet-based systems, but silicon ones are expensive, hence the interest in cheaper alternatives such as glass. Silicon interposers also introduce effects of their own, such as thermo-mechanical stress due to stiffness, requiring extra analysis early in the design process to avoid problems requiring rework.
Wednesday, January 25th
02:00-3:00 PM
B-101: Integration – 1 (sponsored by EMD Electronics) (Partitioning/Integration/Test Track)
Moderator: Milind Weling, Head Neuromorphic Realization, EMD Electronics
Paper Presenters:
Using High-Performance FPGA Chiplets in Heterogenous Systems
Nick Ilyadis, Sr Director Product Planning, Achronix

Optimizing Chiplets Using Heterogeneous Integration and Co-Optimization
Per Viklund, Director IC Packaging, Siemens EDA

Session Description:
Heterogeneous integration is surely the most difficult stage of chiplet development. It involves everything from ensuring that the chiplets actually fit in the package in the right order through power and thermal analysis. The designers must optimize everything together (so-called co-optimization) and manaqe to create a manufacturable device. The system-in-chip itself requires a controller to manage both control signals and data. One option is to use an FPGA chiplet to produce the needed signals. The FPGA approach offers flexibility and simplifies late changes, but also uses chip area and may consume a lot of power.
Wednesday, January 25th
04:30-5:30 PM
A-103: Design – 1 (Design/Packaging/Interfaces/Applications Track)
Moderator: Gordon Allan, Product Manager, Siemens EDA
Paper Presenters:
Bringing Persistent Memory to Chiplets
Bill Gervasi, Principal Systems Architect, Nantero

Energy-Centric AI Acceleration with Chiplet Based Design
Robert Beachler, VP Product, Untether AI

Managing IP During Chiplet Design and Integration
Michael Munsey, Sr Director Semiconductor/IP Solutions, Siemens EDA

Analysis and Verification Platform for Multi-Chiplet Platform Design
John Ferguson, Director Product Management, Siemens EDA

Session Description:
Chiplet-based design requires many new and upgraded tools. The usual analysis and verification platform must be extended to handle multiple chiplets and data must be managed. All of this is complicated by the need to apply everything both to individual chiplets and to the package as a whole. Runtimes will lengthen for entire packages, and the number of runs obviously depends directly on the number of chiplets. Drop-in chiplets would help reduce the strain if methods can be developed for assuring their characteristics and performance.
Thursday, January 26th
09:00-10:00 AM
C-201: Best Packaging for Chiplets Today (Panel) (Panel Track)
Organizer + Moderator: Nokibul Islam, Sr Director Field Application Engineering, JCET Group
Panel Members:
Panelist: Daniel Lambalot, Sr Principal Engineer, Alphawave Semi

Panelist: Laura Mirkarimi, VP 3D Technologies, Adeia

Panelist: Syrus Ziai, VP Engineering, Eliyan

Panelist: Dick Otte, CEO, Promex Industries

Panelist: Mike Kelly, VP Advanced Packaging Technology Integration, Amkor Technology

Session Description:
Packaging is one of the most difficult areas for chiplet designers. Packages must be capable of handling power and heat dissipation, be reasonably priced and small, and be rugged enough for standard applications. Issues of concern include who selects the package and how, which packages are best-suited to chiplet-based designs, what breakthroughs we can expect in packaging over the next few years, and what are the best tradeoffs among size, performance, features, and cost for the many types of packages available today.

 

Trine Pierik

Trine Pierik is the 3D InCites community membership director. She is responsible and committed to…

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