FOPLP

Fifty Shades of Fan-out Discussed at ECTC 2017

The fan-out conversation that started at IMAPS DPC 2017 in March continued this week at the annual Electronics Components Technology Conference (ECTC), which took place in Orlando at the Walt Disney World Swan and Dolphin Resort. The buzz started during the Tuesday evening plenary session, where panelists Douglas Yu, TSMC, Tim Olson, Deca Technologies; Steffen Kroehnert, NANIUM; Rolf Aschenbrenner, Fraunhofer IZM; and Steve Bezuk, Qualcomm Technologies, Inc. discussed the why, how and when of panel-level fan out (PLFO).

The Panel’s Viewpoint
This panel was united in the belief that fan-out will transition from wafer level to panel level in the not too distant future, despite remaining challenges. Offering TSMC’s perspective, Yu remarked that players keep raising the bar on wafer-level fan-out (WLFO) by improving yield, performance, and value, and by reducing cost. While PLFO has yet to be proven in high-volume manufacturing, he sees great potential for it. “There is high risk. But it will be here eventually,” he said.

“Panel and wafer are manufacturing formats, not technologies, and fan-out is a design, not a technology,” explained Kroehnert, to provide some context. “What we are talking about with all fan-out is embedded technology.” And there are many, many variations of fan-out/embedded technologies ranging from low-density to high-density including Infineon’s eWLB, Nepes’ RCP, TSMC’s InFO, Amkor’s SWIFT, Deca Technology’s M-Series, Intel’s EMIB, ASE’s FoCoS… you get the idea.

“We already have fifty shades of fan-out. We don’t need more,” said Kroehnert. Rather, he said we should focus efforts on solving the process and materials challenges to take the WLFO to a larger manufacturing format. The challenges OSATS face with transitioning from WLFO to PLFO he said, is the lack of standards, design constraints, and yield constraints.

Aschenbrenner echoed some of Kroehnert’s sentiments, noting that FOPLP is not merely a geometrical extension of wafer-level. Fan-out is an enabling solution for system in package (SiP) system scaling that closes the gap between silicon scaling and package scaling. Embedded technologies like FO are an integral part of heterogeneous integration.  Calling PLFO “the intelligent combination of wafer-level and PCB processing.” The goal, says Aschenbrenner, is to drive PLFO to similar performance as WLFO but at a lower cost. With redistribution layer (RDL) processes, however, it’s not just about scaling up but involves new process development.

Olson claims that large panel format has the potential to offer a 30% cost reduction because of capital productivity and material efficiency. While the company’s M-Series is built on 300mm round panels (aka reconstituted wafers), Olson says they are moving forward with large panel formats with the support of ASE.

Bezuk noted that Qualcomm has designed WLFO that uses the eWLB process into many smartphones including Samsung, Huawei, and Xiomi models. These are low-density parts with 10-15µm line and space. These parts have been identified as ideally suited for PLFO. The question remains, will high-density fan-out (those that have between 2 and 5µm l/s) find its way to large panel formats?

The Yield Question
Jan Vardaman, TechSearch International Inc. questioned the panel about the importance of yield. They all agreed achieving yields of at least 95% is critical to the success of panel level packaging.

Aschenbrenner noted that yield is a cost question, but that the “sweet spot” for that is not yet clear. Fine line and space require a class-100 cleanroom manufacturing, and currently panel suppliers don’t have that experience, he said.

In addition to contamination from processes and equipment, die shift and warpage that leads to lithography caused defects also impact yield. Olson said that Deca’s approach to fan-out addresses all three. “We believe we will achieve the same yield with large panels as we do with 300mm round panels,” he said.

Yu noted that yield is agnostic of substrate format, and more about reducing defect density. He also said familiarity with core process technologies helps in reducing defect density.

Yu and Kroehnert both cited a lack of inspection tools as a challenge to be addressed, although Yu said we are getting closer. Kroehnert added that OSATS aren’t able to buy the same systems that foundries can, which detect finer feature defects.

The 450mm Question
Subu Iyer, UCLA approached the elephant in the room: asking the panel to comment on the 450mm wafer transition project. I wanted to hear this one, as it seems it could go two ways. Either equipment suppliers can leverage investments made in 450mm platform development to accommodate FOPLP, or they will shy away from risking the investment after being burned by the continued delay in adoption of 450mm wafers.

Yu’s response on behalf of TSMC suggested the former: saying that 450mm is the “low hanging fruit” for a wafer fab, and that technology is proven and established at 300mm that would be adapted “quickly and easily to 450mm as there is already infrastructure that can be used for this purpose.” (I assume he was speaking round vs. square panel format).

Low-Density vs. High Density
I questioned the panel about whether low-density FO, such as the eWLB designed by Qualcomm will ever reach the volumes required to realize cost benefits of going to panel format. I never did get a direct answer to that question. What I did get was a discussion with Olson about what defines high versus low density. His opinion is that both low and high density are suited to PLFO if they are designed as such; at least that’s how it is for Deca. At 3µm l/s, Deca’s M-Series is considered high-density FO and is structurally designed scale to any format: 200mm, 300mm round, or large format panels. Alternatively, while low-density eWLB lends itself to large panel format, at 2µm l/s, Olson said it is not scalable without significant material and structural changes.

The Single Source Debate
Will taking high-density fan-out to panel-level format require multiple supplier sources? This panel didn’t seem to think so. “Single source is not an issue. Because even though there are a lot of tool suppliers, there aren’t a lot of tool suppliers,” he said. “I wouldn’t want to be the OSAT who waits (to develop PLFO) because they will be left behind,” he said. This wasn’t too surprising, as Qualcomm has been driving the development of PLFO. Olson pointed out that relying on small single source suppliers didn’t hold Deca up from realizing M-Series. Additionally, he said at the OSAT level, ASE and Deca are both investing in FOPLP, which comprises multiple sources of technology, and that is enough to make PLFO a reality.

Not if but when?
When asked what he thought the next applications would be for FOWLP and for what devices, Bezuk’s response was cryptic. “The area is ripe. There’s lots of use for it. But I can’t reveal our strategy,” he said.

Moderator, Jean Trewhella GlobalFoundries phrased it another way, asking asked each panelist when they thought FOPLP would become a reality.

“We don’t have the line to do it today,” admitted Bezuk. “If we could do it (FO) in a larger format and get the yield, we’d be doing it today.”

Olson agreed that the need is there, and said they would be ready to manufacture M-Series on large format panels “within a few years.”

Aschenbrenner concurred, saying there are lots of companies worldwide working on it. “I believe in the next two years we will see many new things on this from the substrate-based companies,” he said.

The attendees in the audience, however, were not quite as optimistic as the panelists.  A show of hands revealed that nobody thinks we are ready for panel level packaging. Between 15 and 20 people think maybe we would get there in 3-5 years, and a handful (5 or so) thing we will never see FOPLP.

Suppliers Weigh In
Because the panelists called out material challenges that need to be overcome to get to FOPLP, as well as process control (metrology and inspection) challenges, I spoke to several suppliers to get their perspectives:

Kim Arnold, Brewer Science, addressed the materials challenges, as Brewer specializes in temporary bond/debond processes and material sets for a variety of fan-out process schemes. Deposition is a challenge, noted Arnold. The traditional spin-coat application is not an option for panels. Methods being explored included slot die coating (think squeegee process), spray coating, laminate, and ink-jetting. Warp and bow control will also be an issue. “We are just starting to understand this at the wafer-level. Panel level requires a whole new study. We don’t have all the answers yet,” she said.

Warp and bow control will also be an issue. “We are just starting to understand this at the wafer-level. Panel level requires a whole new study. We don’t have all the answers yet,” she said.

Gilles Fresquet, UnitySC, agreed that inspection and metrology for all types of FO, regardless of manufacturing format, is challenging because there are many process integration schemes to consider. Chips first, chips last, and carrier-based approaches involve different process steps and materials, which translates into different things to be measured and inspected such as mold compound thickness, the interfaces between RDL layers, Cu pillar end points, and more.

Additionally, there are two phases of process control to consider, noted Fresquet. Everything must be measured during the process integration development phase. In phase two, you measure as little as is necessary to control the process and maximize yield.  “A fab’s objective is a low-cost operation,” said Fresquet. “We help our customers come up with the right strategy to get the maximum performance from our tools, and control the process in a way that delivers the best output without putting the process at risk.” While UnitySC offers some game-changing tools that support process control for all these varieties of FO at the wafer level, they have yet to develop a tool for panel-level processing.

Reza Asgari, Rudolph Technologies, says he “truly believes panel is going to be the way to go for FO.” The company invested in developing 450mm tools for both lithography and process control, and even though “that has gone sideways” is not concerned that this will be the case for FO. Additionally, noted Asgari, panel tools aren’t only targeting FO, but also system-in-package for heterogeneous integration applications. “The ROI is higher with fan-out panel packaging than with 450mm,” he said.

A Final Word
As much as these panelists believe that PLFO will be the next big thing for FO manufacturing, I am not convinced it will be realized industrywide in the next few years, if ever, at least not for HDFO. Consider that it’s not only the challenges of one type of FO that need to be addressed but many types. And each needs to generate enough volumes to justify supplier development of tools and materials to build an infrastructure to support it industry wide. The question we should ask is whether Qualcomm, TSMC, ASE and Deca together will create enough of a demand for the equipment suppliers to risk investment in the tools to build the infrastructure for their collective technologies? Sounds an awful lot like the 450mm scenario. But it’s something to think about. ~ FvT