3D EDA tools

Executive Interview: Si2 Aims to Boost Confidence in Designing 3D ICs

Executive Interview: Si2 Aims to Boost Confidence in Designing 3D ICs

There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D IC devices are matured and ready for production. However, the jury is still out in the design community because designing 3D ICs still poses a challenge. Si2 has set out to change that and bring confidence to the minds of chip and system-level designers. Steve Sc... »

3D By Design: Exploring Viable Path Finding

3D By Design: Exploring Viable Path Finding

Fruitful path finding eventually identifies solutions that are viable for mechanical, electrical, thermal, and cost (METC) requirements. Hopefully, more than one viable solution is found to offer a backup in case something was overlooked during exploration or your supply chain can no longer support your needs. Even if you need to re-explore due to changing situations, path finding is still faster... »

Courtesy of Cadence - 3D By Design

3D By Design: A Blog By and For the 3D Design Community

Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference, where I moderated a session on system on chip (SoC) design complexity, and ... »

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

 Are slow standardization and CAD-tool development hindering the progress of 3D IC design and integration? This was the topic of discussion during the Friday 3D Workshop at DATE 2014, which took place this year in Dresden, March 28, 2014. I was invited to moderate this panel discussion, which featured panelists from EDA suppliers, industry, and academia. We wanted to mix it up a bit and involve ... »

TSensors Summit

Catching Up With Steve Breit, Coventor, at the TSensors Summit

A journey of a trillion sensors begins with a single step. The TSensors Summit, held at Stanford University on 23 – 25 October 2013, was a showcase for the ideas and strategies that will lead the electronics industry to produce very high volumes of Microelectromechanical Systems (MEMS)-based sensors for use in new applications likely to enter the market in the coming decade. There are currently ... »

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

Despite the chilly San Francisco morning temperatures, a sizable crowd of 2.5D and 3D enthusiasts gathered at the Impress Lounge to witness the inaugural 3D InCites Awards Breakfast, held July 11, 2013 during SEMICON West. For me, it was especially significant as it marked four years since I first launched 3D InCites at SEMICON West 2009. I felt truly honored to be surrounded by such industry elit... »

Synopsys: Galaxy Implementation Platform

Synopsys: Galaxy Implementation Platform

Product Description Synopsys’ Galaxy™ Implementation Platform is the industry’s leading solution for IC implementation and signoff. Now available with powerful automation for multi-die implementation and foundry certified design flows, Galaxy provides a silicon-proven path to successful implementation of 3D-IC stacked die and silicon-interposer based 2.5D systems. Testimonial Following colla... »

Apache Design: RedHawk-3DX

Apache Design: RedHawk-3DX

Product Description Apache Design’s fourth-generation RedHawk™-3DX simulation software technology extends previous generations’ capabilities to address sub-20 nanometer (nm) designs with 3+ gigahertz performance and billions of gates. It is also architected to support the simulation of emerging chip and packaging technologies using multi-die three-dimensional ICs (3D-ICs) for smart electroni... »

Mentor Graphics: Calibre

Mentor Graphics: Calibre

Product Description Calibre enables signoff verification of chip stacks with flip chips, silicon interposers and through-silicon vias (TSVs). Verification of individual dies is followed by checks on the interfaces between dies, including dimensional checks (bump alignment and rotation), connectivity checks (LVS), and parasitic extraction (PEX) using a special 3D-IC rule file. Testimonial Calibre a... »

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs

WILSONVILLE, Ore., May 20, 2013—Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzaron’s 3D IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the us... »

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