Synopsys_3D-IC_Routing_Example_061813Product Description
Synopsys’ Galaxy™ Implementation Platform is the industry’s leading solution for IC implementation and signoff. Now available with powerful automation for multi-die implementation and foundry certified design flows, Galaxy provides a silicon-proven path to successful implementation of 3D-IC stacked die and silicon-interposer based 2.5D systems.

Following collaborations with leading foundries and semiconductor design companies in the FPGA, memory and systems markets, Synopsys introduced an enhanced version of its popular Galaxy Implementation Platform for 3D-IC and 2.5D-IC implementation. Galaxy’s IC implementation and signoff toolset, including IC Compiler™ place and route, PrimeTime® signoff, StarRC™ parasitic extraction, HSPICE® circuit simulation and more, now provide engineers with an evolutionary path to 3D-IC design without requiring major changes to their design environment. For example, in IC Compiler, we complemented our Manhattan router, used to route the silicon interposer interconnect, with a 45-degree-capable router to handle the dense redistribution layers. In HSPICE, we expanded the capabilities of both the modeling language and the simulation engine to enable the co-simulation of different modules using different process technologies and operating conditions to enable multi-die simulation. In StarRC, we enhanced StarRC to support the extraction of additional features required in a 3D-IC system, including TSVs, front and back-side RDLs, and microbumps to improve the accuracy of circuit analysis. the Galaxy platform is certified by TSMC and GLOBALFOUNDRIES for use with their 2.5D-IC technology.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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