I just took a good look at the line-up for the 3-D Architectures for Semiconductor Integration and Packaging, coming up December 9–11, 2009, and I think I might have died and gone to 3D heaven. You want to know who the movers and shakers are in this space? They’re all here, and they’ll be addressing all the critical issues we’ve been hearing so much about: design, test and thermal issues, wafer handling, supply chain infrastructure, and more. I mean, just look at this line up of companies and organizations speaking at the event: Alchimer, ALLVIA, Amkor Technology, ASE Group, BeSang, Cadence Design Systems, CEA-Leti MINATEC ®, EV Group, IBM, Intel, Ipdia, Mentor Graphics, Microelectronic Consultants of North Carolina, Micro Magic, MIT Lincoln Laboratory, North Carolina State University, R3Logic, RTI International, Soitec, STATS ChipPAC, ST-Ericsson, SUSS MicroTec, TOK America, TSMC, TechSearch International, Tezzaron Semiconductor, University of Rochester, University of Texas, Yole Développement, and Ziptronix; literally covering this topic from A-Z. I get excited when I see that companies and technologies we’ve been following closely on 3D InCites are participating. For example, Claudio Truzzi from Alchimer, who has had several lively discussions about Alchimer’s technology with me, and more recently, Ed Korczynski; will talk about production processing of high aspect-ratio TSVs. Thorsten Mathias, of EV Group, who also participated in a discussion on 3D InCites about integrating TSV processes, will discuss thin wafer handling and chipstacking technologies for 3D integration. Wilfried Bair, of SUSS MicroTec will look at the business side of thin wafer handling, discussing efficient capex utilization. Bernard Aspar, of SOITEC, will present some of the technologies he briefed me on when I visited the company in October on my Tour de France in 3D; as will Mark Scannel, of CEA-Leti. I’ll be looking forward to seeing a guest blogger Yann Guillou of ST Ericsson, who will be talking about the implications 3D integration has on the wireless IC market. And it will be good to reconnect with Bob Patti of Tezzaron, who shared the spotlight with me on the Brightspots 3D Panel in July. Bob will be sharing his experiences on commercialization of 3D integration. But I get even more excited to see companies presenting that I haven’t been following closely, because it offers the opportunity to make new connections, and provide even more information to our readers on 3D InCItes. I’m talking about companies like BeSang, TOK, and Ipdia (which is a recent spin-out of NXP semiconductors). I’m also looking forward to updates on 3D from the perspective of the design community: Mentor Graphic’s Frank Schellenberg will talk about the impact 3D has on scaling, modeling insertion for 3-D (design, extraction, interconnect and test); and design integration for 3D. Lisa McIlrath of R3Logic will talk about EDA requirements for the 3D roadmap. And Vassilios Gerousis, of Cadence, will discuss the companies work with a 3-D thermal analysis application. See what I mean? This is a not-to-be-missed 3D event. I was lucky enough to score a press pass to this one. I realize travel budgets are tight, but if you really want to know what’s going on in 3D you’ll do whatever it takes – beg, borrow, steal – but be there. — F.v.T P.S. – Just got a reminder in my inbox – early registration discounts still apply until November 24th.