CHIPS

The Truth About Moore’s Law is Revealed at 3D ASIP 2017

The Truth About Moore’s Law is Revealed at 3D ASIP 2017

I’ve long held the belief that when it comes to reading scholarly works, very few people read the entire paper. At best, they read the title, introduction, and conclusion. At most, they skim the rest. Last week at 3D ASIP 2017, my suspicions were confirmed, when it was revealed by Dan Green, DARPA, that if the powers that be had bothered reading to the top of Page 3 of Gordon Moore’s “Crammi... »

Sir Walter Raleigh towered above the 50th IMAPS Symposium

Sir Walter Raleigh towered above the 50th IMAPS Symposium

Almost 500 years ago Walter Raleigh was born in England, rose rapidly in the favor of Queen Elizabeth I and was knighted in 1585. In 1587 he initiated the founding of Raleigh. Last week he welcomed – appropriately dressed – about one thousand semiconductor experts to the 50th International Symposium on Microelectronics at the Raleigh, NC, Convention Center (Figure 1). If you look closer at thi... »

EV Group Optimizes Resist and Lithographic Processing for Plasma Dicing for Advanced Semiconductor Packaging Applications

EV Group Optimizes Resist and Lithographic Processing for Plasma Dicing for Advanced Semiconductor Packaging Applications

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it is demonstrating optimized pre-processing solutions for the implementation of plasma dicing for advanced semiconductor packaging applications. EVG’s latest products and process development services support this emerging semiconductor back-end fa... »

Outlook 2017:  SoC Goes on a Dielet

Outlook 2017: SoC Goes on a Dielet

It’s 2017, and system-on-a-chip (SoC) is headed for a dielet. At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA. SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment. For example, the old ISO defect density rules from my early I... »

System-level Scaling: UCLA’s Answer to Extending Moore’s Law

System-level Scaling: UCLA’s Answer to Extending Moore’s Law

“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about scaling the system.” ~ Excerpt from the letter to attendees of the CHIPS kick-off meeting at UCLA. ... »

Hey Data Guys, Show Us the Money!

Hey Data Guys, Show Us the Money!

I spent last week attending two separate events: the opening of the Center for Heterogeneous Integration and Performance Scaling (CHIPS) at UCLA, and The MEMS Executive Congress, in Napa. I came away from both events with some interesting takeaways on new technology developments, which I plan to dive into and share in the coming week. But more importantly than that, I came away with some perceptio... »