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The market for high bandwidth memory (HBM) is projected to grow 49% in wafers, including DRAM and logic layers, from 2020 to 2024. Growth is driven by increased adoption in high-performance computing such as AI, networking, graphics, and future server processors. Solutions to package HBM plus logic include silicon interposers...
Because IMAPS is a society, there is a strong community aspect to its events. It was good to see that captured at this year’s symposium. I really enjoyed attending the live versions of the Society Awards presentation and the Diversity and Inclusion Roundtable. I also popped into the Student-Industry Roundtable...
In September of 2018, I spoke with KLA’s Stephen Hiebert and Pieter Vandewalle about the changing advanced packaging landscape, and the need for better process control that inspired the company’s foray into the advanced packaging space. With the introduction of its IC packaging portfolio that comprised the Kronos™ 1080 and...
I was halfway through my post about my day at Virtual SEMICON Taiwan, when I realized that to do the Global SiP Summit justice, meant it would need its very own post. The live version of the event spanned three full days. That’s a lot of content. While the on-demand...
This week we continue our look at ECTC 2020. imec and SPTS Collaborate on Nano-TSV Processes As part of our IFTLE theme of advanced packaging and interconnect going submicron, let’s look at the imec (long renowned for both their front end and back end work) presentation “Extreme Wafer Thinning and...
Over the past few years, we’ve seen KLA evolving from its origins as a process control company focused on front-end solutions, to a more holistic organization that extends its reach into more segments of the electronics chain, like, packaging, display, and components. The ICOS inspection product line got it pointed...
If TSMC’s Doug Yu wrote a rap song, the title would be “HIT IT!” He’s been on a roll lately, evangelizing heterogeneous integration technology (HIT) as the new path going forward for the semiconductor industry. In fact, the ECTC 2020 keynote is Yu’s third keynote presentation at key h this...
Severine Cheramy has devoted her career to developing 3D integration technologies and bringing them to market. She was the first person to show me what a TSV wafer looked like when I visited CEA-Leti’s cleanroom in 2009 during my Tour de France in 3D. At the time, she was a...
At the latest MEPTEC Luncheon, held February 5, 2020, and hosted by SEMI at its Milpitas HQ, Google’s Dr. Preeti S. Chauhan, Technical Program Manager for Data Center Quality, presented her perspectives on the benefits and challenges of advanced IC packaging technologies. Considering that Alphabet, Google’s parent company, controls about...
The November Issue of Chip Scale Review contains some interesting advanced packaging information that is worthy of sharing in IFTLE: the cover story on fluxless µbumping by ball placement, and Yole’s look ahead at stacking technologies. Fluxless µBumping by Ball Placement CC Dong from Air Products examined fluxless micro ball...
