If TSMC’s Doug Yu wrote a rap song, the title would be “HIT IT!”  He’s been on a roll lately, evangelizing heterogeneous integration technology (HIT) as the new path going forward for the semiconductor industry. In fact, the ECTC 2020 keynote is Yu’s third keynote presentation at key h this year on this particular topic. In-person, he presented the keynote at the 3D Summit in Dresden in January, which Steffen Kroehnert covered for 3D InCites. Due to COVID-19, he delivered the IMAPS Device Packaging Conference keynote via WebEx. Despite the valiant effort of the IMAPS team to provide adequate audio, I could only catch about every fourth word. Thanks to Jan Vardaman for capturing those highlights here.

I am happy to report that not only is this pre-recorded presentation clear and precise, but it was also nice to listen to it without the ongoing chatter of the luncheon in session, as is usually the case for the ECTC Keynote. As he began his talk, Yu noted that he hoped the novelty of the this virtual event made the talk more memorable. So far so good!

The HIT Back Story

The official title of Yu’s presentation is Innovative Heterogeneous Integration Technologies Initiate a New Semiconductor Era. He starts off presenting a detailed history of the heterogeneous over the last 10 years. For newcomers to the industry, Yu provides a great summary of what’s driving the transition from system-on-chip (SoC) scaling, to heterogeneous integration. It also provides the back story of HIT development, from 2.5D interposer approaches using through-silicon vias (TSVs) to TSV-less approaches such as fan-out wafer-level packaging (FOWLP), to the latest chiplet solutions including Intel’s Foveros and EMIB (Figures 1 & 2).

HiT

Figure 1: Heterogeneous Integration with TSV throughout the years. (Courtesy of Yole Developpement and TSMC)

HiT

Figure 2: TSV-less heterogeneous integration. (courtesy of Yole Developpement via TSMC)

Yu also details TSMCs offerings in this space, including its latest chiplet solution, system-on-integrated chip (SOiC), for which TSMC won the 2020 3D InCites Device of the Year and Doug Yu won Engineer of Year awards If you haven’t had the chance to hear him speak on this topic, I recommend you register and listen to this 40-minute talk. No time to listen to the whole thing? Below I’ve captured what I consider to be the highlights, lowlights, and ah-ha moment.

Highlight 1: 3D Interconnection Density (3DID)

It took 30 years to evolve from the first digital computer to the first portable computer, 10 years to evolve from the first mobile phone to the first smartphone, and one year to take autonomous vehicles testing in the desert to an urban environment. With market drivers like artificial intelligence (AI) and 5G, Yu says we can expect a drastically accelerated rate of change.

Figure 3: How the rate of technology change has accelerated over the last 600 years. (Courtesy of TSMC)

“Societal expectations from semiconductors and information technology (IT) are demanding and insatiable,” said Yu. “Moore’s Law needs a huge investment to continue. Many players are looking for other solutions, that’s where HIT comes in. Costs will go up if we continue following traditional SoC scaling.”

Using chiplet technologies for further scaling achieves cost advantages, because yield increases and die cost decreases. Yu explained that cost savings are more pronounced with large SoC sizes and advanced technology nodes, where base wafer cost is higher. By bringing chiplets together and making inter-chip interconnects shorter, he says we can mimic SoC scaling cost-effectively. Yu defines this as a 3DID approach, which is enabled by bumpless hybrid bonding technologies.

Lowlight: An Infomercial for TSMC Products

In my opinion, a keynote should never be used as an opportunity to deliver an infomercial.

A good chunk of this presentation did just that, so I won’t go into those details. If you’d like to learn more, again, register and watch the presentation.

A-Ha Moment: Poetic License?

For today’s A-Ha moment, I need to call out Dr. Yu on his math. Early on in the talk, he states: “What makes the turning point so special? That was when Moore’s Law started; just about when our ECTC started. Moore’s Law has driven the semiconductor industry for about 70 years.”  Hold on, WHAT?  Moore’s Law started in 1965 – a mere 55 years ago. Moore’s Law and I were born the same year, and I’m not even CLOSE to 70. Let’s just chalk it up to the poetry of putting ECTC and Moore’s law together on the timeline. Moving on.

Highlight 2: HIT Makes Packaging Engineers the MVP

Someone once told me that the best way to deliver criticism is to use a “compliment sandwich.”  Start with good points, insert constructive criticism, end on a high note. So that’s why I’m finishing with a highlight. Yu wrapped up his keynote with an inspirational message for his fellow packaging engineers.

Never has there been a better or more exciting time to enter into the field. No longer are packaging engineers relegated to defense roles, fixing problems. Yu says innovative HIT like 2.5D interposers, redistribution layer (RDL) interposers, and bumpless 3D ICs are eliminating chip-package-interconnect issues that have plagued packaging engineers for years. While the traditional roles are still important, the job is becoming more exciting.

“Today those roles are still essential and important. However, we have changed our packaging engineers’ longtime roles from defense to offense by those innovative HITs,” noted Yu. “We the packaging engineers, like a talented basketball player, can make a good defense play, force a turnover, execute an excellent offensive play, and get more fun out of the game.”

Yu hopes to inspire current and new engineers’ path as HIT offers a path forward. He says everyone in packaging is capable of great innovation that leverages core competencies to achieve higher goals that make the world a better place and make their jobs more exciting and rewarding. ~ FvT

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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