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The monthly MEPTEC Luncheons at SEMI in Milpitas focus on microelectronics packaging and test topics. Javier DeLaCruz, Xperi’s VP of Engineering, presented at the latest Luncheon on January 8 a joint study with eSilicon. It compared how die-to-wafer (D2W) bonding, using Direct Bonding Interconnect (DBI) technology, compares with traditional (2.5/3D-IC)...
At Laser World of Photonics in Munich, Finetech will present the successor of its acclaimed sub-micron bonder for research and development. Technological innovations make the high-precision placement and assembly system the ideal starting point for cost-efficient and fast development of optoelectronic products. As a manufacturer of micro assembly equipment and...
The annual International Electron Devices Meeting (IEDM) presents the latest developments in electronic device technologies focused on advanced scaling, heterogeneous integration, quantum computing, and wide bandgap devices. Among several excellent papers on 3D integration were two papers on 3D sequential integration, long the holy grail of 3D integration because of...
SAINT-JEOIRE, France – Jan. 15, 2016 – SET, Smart Equipment Technology, the leading supplier in high-accuracy die-to-die and die-to-wafer bonders, today announced its participation in the 3D integration consortium of IRT Nanoelec, which is headed by CEA-Leti. SET joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D die-to-wafer stacking...
A second side trip on the way to DATE 2015 brought me back to Nimes, France to check up on activities at Fogale Nanotech since last year. I was reminded once again, that Fogale isn’t just a semiconductor equipment supplier. Its core competencies are optical and capacitive sensing technologies, and thanks to...
Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These...
SETNA, in conjunction with Research Triangle Institute (RTI), has developed a binary alloy (Silver-to-Indium) bonding system for 3D IC assembly that can be compression-bonded at room temperature. Following 3D IC chip stacking, the Ag-In structure is annealed in the solid-state (no melting) to form an Ag₂In interconnect which is stable...
While other presenters for the 2013 3D ASIP session, “Evolution of 3D Technologies and Market Trends” took a more conventional approach to reporting the status of 3D integration, Jan Vardaman, TechSearch International gets the prize for originality and humor for playing the role of “professor” and delivering the 3D readiness...
When it comes to 3D chip stacking, chip-to-wafer (C2W) processes have proven to be the way to go for stacking known-good-die (KGD) for best yields, or if the dies being stacked are of different size. Unfortunately, sequential C2W processes have historically been time consuming, achieving low throughput; making it a...
Rudolph Technologies, Inc., provider of process characterization equipment and software for wafer fabs and advanced packaging facilities announced that it will collaborate with a process tool supplier and an IC device manufacturer in the development of 3D advanced semiconductor packaging applications. The development effort involves the integration of defect inspection...
