Rudolph Technologies, Inc., provider of process characterization equipment and software for wafer fabs and advanced packaging facilities announced  that it will collaborate with a process tool supplier and an IC device manufacturer in the development of 3D advanced semiconductor packaging applications.

The development effort involves the integration of defect inspection with a de-bonding tool.  Manufacturing efficiencies, along with the ability to handle ultra-thin wafers, necessitates the integration of inspection in de-bonding applications. Rudolph is bringing its inspection technologies to this three-way collaboration for an integrated process control solution.

During the manufacturing process of these advanced packages, high-resolution edge inspection helps to ensure that trimmed wafer edges do not have any hairline cracks, chips or mechanical flaws that may lead to wafer breakage during the thinning process. This edge inspection can now be performed on Rudolph’s F30 module, and also includes the wafer notch area which is especially prone to mechanical failures.

After wafer thinning, the module may perform a frontside inspection to verify that all of the temporary bonding material has been thoroughly removed.  A backside inspection of a flipped wafer can also be performed to ensure that the thinning process did not mechanically damage the surface and that the TSV contact areas have been properly processed.  Wafer disposition after inspection may require re-work and this decision can be made quickly and automatically for high-volume manufacturing applications through an industry standard communication protocol directly to the process tool.

“Rudolph Technologies is pleased to participate in such a forward-looking program with two of the industry’s leading technology drivers.” said Ardy Johnson, Rudolph’s vice president of marketing and product management.

Advanced 3D stacked packaging is driving the need for new process tool development that includes temporary wafer-carrier bonding and de-bonding applications. These process steps are paramount to support the necessary wafer thinning that is critical in the development of next generation miniaturized devices.

 

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