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Commercial Times reports that TSMC’s Arizona wafer fab, Fab 21 Phase 1, has officially entered mass production on its 4nm process. Monthly capacity is expected to reach 30,000 wafers by mid-year. Construction of Fab 21 Phase 2 and Phase 3 are set to proceed this year and next, with fab...
Hello, I am Mandy Perdok. I am 20 years old and live in Milsbeek in the Netherlands. My hobbies include playing Netball (Team Sport), training/coaching the Netball youth team, and traveling. As a third-year student majoring in Chemical Engineering at the Fontys Hogeschool Eindhoven of Applied Science, I am completing...
LITHOSCALE® incorporates EVG’s MLE™ (Maskless Exposure) technology to bring the benefits of digital lithography to a wide range of applications and markets EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the LITHOSCALE® maskless exposure system – the...
The 54th Design Automation Conference (DAC 54) at the Austin Convention Center was very different, compared to the last several years’ events. Walking the exhibition floor, listening to keynotes, SKY talks and CEO interviews I got the following key impressions: While still representing a big part of the audience, the...
A few weeks ago, Tezzaron announced its latest industry first: an eight-layer 3D IC wafer stack containing active logic, built at its fab, Novati Technologies, a global nanotechnology development center located in Austin, TX. Novati is clearly on a roll, because today they added another industry first to their product...
In June 2014, SPTS co-produced a webinar with Ron Huemoeller of Amkor, titled “2.5D and 3D Packaging at the Tipping Point.” We forecasted that significant product announcements would be made over the next 18 months and we were right; sk Hynix, Samsung and Micron all announced readiness for their 3D stacked memory...
That Jan Vardaman, she’s so clever! I just finished reading her column on ECTC 2013 in Printed Circuit Design and Fab, and thought her quippy, Las Vegas-y references in the opening paragraph were right on the money. Vardaman’s take on ECTC was similar to my own, discussed here in my...
Day Two of the European 3D TSV Summit dawned bright and clear, with such a spectacular view of the nearby French Alps that it took real commitment to stay indoors and focus on the task at hand. But I have to admit that for the most part, it was worth...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
Sometimes I get so caught up in following the progress of 3D IC with TSV that I lose sight of what else is going on in the 3D space.That is until something like STATS ChipPAC’s announcement that they are ramping to volume production with first-generation eWLB technology hits my inbox....
