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Adeia Wins ECTC Award for Paper on “Fine Pitch Die-to-Wafer Hybrid Bonding”

SAN JOSE, Calif.—July 10, 2024—Adeia Inc. (Nasdaq: ADEA), a leading research and development and intellectual property licensing company known for bringing innovations in the semiconductor and media technology sectors to market, was awarded Best Session Paper at the 2024 Electronic Components and Technology Conference (ECTC) held in Denver, Colorado on...

When Plasma Matters

As the company boasts some of the most advanced plasma equipment in the industry, CCO Peter Dijkstra discusses how Trymax Semiconductor Equipment B.V. (Trymax) has achieved this unique position. Amongst many titans of the semiconductor manufacturing industry in the Netherlands, Trymax Semiconductor Equipment B.V. (Trymax) is the company of choice...

ClassOne Technology and Fraunhofer ENAS to Collaborate on Hybrid Bonding for Advanced Imaging Devices

Partnership will leverage firms’ respective heterogeneous-integration proficiencies to focus on development and optimization of full process-integration schemes for diverse high-density pixel array applications  Kalispell, Mont. – June 2, 2022 – ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today announced it is...

Micross Components Acquires Semi Dice

Melville, NY (July 1, 2021) – Micross Components (“Micross”), a leading provider of high-reliability microelectronic product and service solutions for aerospace, defense, space, medical and industrial applications, today announced the acquisition of Semi Dice, LLC (“Semi Dice”), a global provider of high-reliability die & wafer products and value-added services. The...

Smoltek demonstrates CNF-growth on a 200mm silicon wafer

Last week our awesome and hardworking R&D-team managed to demonstrate CNF-growth on a 200mm silicon wafer in the Chalmers MC2 150mm lab in Gothenburg. This great achievement opens up new methods for better and simpler prototype manufacturing for customers utilizing 200mm production processes.

SPTS Debuts Low-Temperature PECVD Technology for 3D-IC

SPTS Technologies has launched its low temperature plasma-enhanced chemical vapor deposition (PECVD) solution for via-reveal passivation in 3D-IC packaging applications. Already proven in 300mm volume production fabs, the Delta fxP® PECVD system deposits dielectric layers onto bonded substrates at wafer temperatures below 200°C,  with throughputs up to twice that of...

Tips on Modeling Warpage for 3D ICs

This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...

SEMI International Standards Program Forms 3D Stacked IC Standards Committee

SEMI announced today the formation of a Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee. 3DS-ICs are composed of a stack of two-dimensional die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration methods like wirebond and flip chip have been in production...