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EV Group Brings Revolutionary Layer Transfer Technology to High-volume Manufacturing with EVG®850 NanoCleave™ System

Dec 07, 2023

Infrared laser cleave technology enables ultra-thin-layer transfer from silicon substrates with nanometer precision, revolutionizing 3D integration for advanced packaging and transistor scaling FLORIAN, Austria, December 7, 2023—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG®850 NanoCleave™...

Cu-Interposer Drives Connectivity to the Next Level

Nov 22, 2019

Plan Optik AG, the leading manufacturer of customized wafers from glass, quartz or glass-silicon compound materials has launched its new Cu-Interposer technology at SEMICON Europa 2019. The progressive miniaturization, increasing integration density, and requirements for more powerful signal routing create the need for 3D integration. Interposer technologies for rewiring have...

A Race to the Finish: Announcing the Winners of the 2019 3D InCites Awards

Mar 01, 2019

The 2019 3D InCites Awards vote was a nail-biter right up until the end.  While some categories seemed almost predictable from start, others were neck-and-neck, with the front runner changing on a daily basis. What was most exciting to me, however, was how many new participants we had, and how...

HPC, AI and Datacenters: the 2.5D & 3D Stacking Technologies Playground

Feb 13, 2019

“2.5D and 3D stacking technologies are the only solution that meet the required performance of applications like AI[1] and datacenter as for today”, confirms Mario Ibrahim, Technology & Market Analyst from Yole Développement (Yole). Stacking technologies are used in a variety of hardware, including 3D stacked memory, GPU[2], FPGA[3], and...

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

Sep 01, 2018

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move...

Rudolph Announces Multiple Customers’ Acceptance of its Firefly Inspection System

Sep 14, 2017

Wilmington, Mass. (September 12, 2017)—Rudolph Technologies, Inc. (NYSE: RTEC) announced today that its Firefly™ Inspection Systems, shipped to fulfill previously announced orders from multiple semiconductor manufacturers, are now qualified for production. The Firefly Inspection Systems provide high-resolution visual and non-visual inspection in a variety of advanced packaging processes, including fan-out...

Deca Technologies Sees Promise in FOWLP for 2016

Jan 14, 2016

According to TechSearch International, we can expect to see 87% CAGR for fan-out wafer-level packages (FOWLP) over the coming 3 years. This demand is driven by a combination of several factors. Primarily there is great potential for the advanced capabilities of FOWLP to provide cost-effective system-level solutions for mid- to...

Assembly Design Kits are the Future of Package Design Verification

Aug 03, 2015

Unlike the traditional system-on-chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and assembly houses have no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturability and performance...

Applied Materials Announces Atomic-Level Film Treatment to Reduce Chip Power Consumption

Nov 29, 2011

Applied Materials, Inc. today announced a breakthrough technology for reducing power consumption in semiconductor chips with its new Applied Producer® OnyxTM film treatment system. By optimizing the molecular structure of the low k films that insulate the miles of wiring, or interconnects, on each chip, the Producer Onyx system enables customers to continue...

Is the Bloom off the 3D TSV Rose?

Oct 15, 2010

So I’m sitting here back at my desk, sifting through my pile of notes from this week’s adventures at the 2010 International Wafer Level Packaging Conference in Santa Clara, CA, trying to figure out what to write about first. Between chairing sessions, conducting interviews, attending keynotes and panels, and just...