According to TechSearch International, we can expect to see 87% CAGR for fan-out wafer-level packages (FOWLP) over the coming 3 years. This demand is driven by a combination of several factors.
Primarily there is great potential for the advanced capabilities of FOWLP to provide cost-effective system-level solutions for mid- to high-pin-count components by addressing the size and performance requirements. In addition to the high-volume demands from the mobile wireless and IOT segments, the FPGA market is also seeing the benefits this technology can provide.
Additionally we see multiple opportunities for multi-die solutions from customers who are looking for an alternative to stacked-die packaging—the driving force being reductions in the footprint and thickness. There are multiple market segments where this feature is advantageous, but clearly the mobile segment will be a key sector. Furthermore, the wearables and IoT markets are seeing that the benefits of FOWLP, combined with the elimination of the substrate, permit greater flexibility in supporting the OEM’s unique requirements.
Why the seemingly sudden takeoff of FOWLP after years of delayed adoption? As scaling drives finer features from chips into the package requirements, companies are asking for fine-line and space geometries beyond what is typically available within substrates. This is where the use of wafer-level process techniques—which will allow geometries down to 2µm line and space—is proving to be the preferred option.
At Deca Technologies, our large-panel manufacturing capabilities, combined with our proprietary Adaptive Patterning™,—which allows for in-process compensation of die shift—differentiates us from other players in the FOWLP market. Ever since we introduced the M-Series™ with Adaptive Patterning, we have been fielding inquiries from OEMs about system-level opportunities using our technology.
All this adds up to a very promising year for FOWLP and Deca Technologies. ~ G. Pycroft