So I’m sitting here back at my desk, sifting through my pile of notes from this week’s adventures at the 2010 International Wafer Level Packaging Conference in Santa Clara, CA, trying to figure out what to write about first. Between chairing sessions, conducting interviews, attending keynotes and panels, and just generally catching up with everyone, my head is once again crammed with information and more than a few perceptions I feel compelled to share. So here’s how it’s going to go. I’m going to start with my general thoughts and perceptions, and the rest will follow over the next week or so.
While Tuesday night’s kick-off by Peter Ramm, of the Fraunhofer EMFT in Munich drew a sizeable audience to hear what he had to say about the European 3D technology platform, as did Rozalia Beica’s closing talk on EMC3D progress in addressing TSV technology challenges, the rest of the 3D sessions seemed to have a lot of empty chairs. Meanwhile next door in the wafer level packaging (WLP) track they were whooping it up to a full house.
This was the first time in a couple years that 3D track sessions hadn’t been standing room only, and I have to admit, it was a new experience for me and I was more than a little envious. But I guess when I think about it, it was to be expected. TSVs have definitely hit that awkward stage. While the latest developments are vital to market adoption of TSVs, they aren’t quite as sexy as they were when the news was about technology breakthroughs. There were more presentations than ever before addressing design, reliability, inspection, failure analysis, test and test standards for 3D ICs. And while they may not have been the crowd pleasers we thought they would be, I was glad to see that these previously identified roadblocks are not only being addressed and resolved, but that those working in those areas were enthusiastically sharing their knowledge with the packaging community.
So while we seem to be in a wait-and-see holding pattern with 3D ICs, wafer level packaging and 3D WLP packaging technologies are taking off and providing some immediate solutions. TechSearch’s Jan Vardaman notes that WLP is pervasive throughout our industry and increasing over time. The star of the WLP show is fan-out WLP (FO WLP) and more specifically Infineon’s eWLB technology. Vardaman reports that STATS chipPAC has shipped 35M eWLB packages and more versions of FO WLP can be expected soon including from other manufactures driven by wireless applications. ASE has licensed eWLP; Nepes bought the RCP line from Freescale and is developing a 3D SiP solution; and Infineon is working to develop a PoP version in its next-generation eWLB.
Several people pointed to causes for this shift. Ramm notes that of all the drivers for 3D integration, cost and performance top the list. 3D WLP addresses both of these sufficiently for the moment. He pointed out that CMOS image sensors are currently the only product on the market using TSVs, and that while there are many prototypes and demonstrators of various applications, it will be some time before they appear in more products. He said 2012 could be a crucial year for real TSV 3D technology, but it’s more likely that we’re a full decade away from product.
Gartner’s Jim Walker concurs on the cost driver, and added time-to-market to the mix. He said that silicon integration methods take too long, and that packaging is becoming the integrator. “We are solving problems via 3D and all various derivatives of 3D. Packaging is adaptable to time to market.” notes Walker.
So at the risk of mixing my metaphors, the bloom maybe temporarily gone, but I’m thinking it’s just a case of normal technology growing pains. And in any case, TSV or not, “3D” is still the operative word.
But don’t take my word for it. I’d love to hear from others who attended IWLPC. Please, share your perspectives here – F.v.T.
Hi Francoise,
I decided to sit out IWLPC because of schedule clash even though I am local to the Silicon Valley; the SCV chapters of IEEE CPMT, Comsoc, Circuits & Systems all had several coincidental events on the 12th & 13th including some on 3D topics, nanopackaging, from the director of PRC at Georgia Tech.
Contrary to your observations, there are several parallel efforts that are underway by standards bodies, interest groups and others where I see active participation from both EDA companies, IDM’s, packaging houses and product design companies. GSA’s 3D standardization meeting for example saw active participation last month at Synopsys and I have seen many attendees from that at other events since.
I don’t believe TSV’s will take another decade to mature. The progress you see in WLB/WLP’s and its variants is due to the technology that is available today. The packaging houses are leading the way in process and assembly development while the product owners are getting by with adhoc methods for design verification and simulation. This can not be applied to the 3D designs using TSV’s. The industry is still far from realizing an ‘acceptable’ design flow for 3D and the existing tools are slowly making progress to address the market need.To that end, the packaging houses have a lot to offer to guide the EDA companies.
While capabilities (not to mention the sexiness!) that TSV’s add to a design may be appealing, cost will be the deciding factor. Until we address that, 3D TSV’s may remain accessible to only few players.
Dr. MP DivakarConcurrent Analysis Corporation
Dr Divakar Thanks for sharing you’re insight. I guess the current level of excitement depends on the audience you’re drawing from, in the case of IWLPC it was mostly those in semiconductor packaging, whereas at the GSA 3D meetings, the audience is from the design community where 3D TSV is currently the topic du jour as packaging and semi guys clamor for the right tools.
I certainly hope you’re right about TSVs maturing sooner than in 10 years.
Hi Francoise, I had a schedule conflict and could not attend. Couple of unrelated items that I see:
– TSV : There is a lot of effort going into Si Interposer. So you will see real stacked products using current dies (no vias) connected through vias in a Si Interposer. Definitely by year-end 2011
– Vias : Even power devices are using Cu filled vias. Not for die-stacking, but power/ground.
BTW we are VERY involved with ALL eWLB producers and lets just say other OSATs are trying to get in.
Thanks for the summary.
Rajiv
VP Business Development,
Rudolph Technologies