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Solving the AI Puzzle

An AI package is like a puzzle made up of individual pieces of different sizes and shapes, each one essential to the final product. Together, these pieces are typically integrated into a 2.5D IC package designed to reduce footprint and maximize bandwidth. A graphic processing unit (GPU) and multiple 3D...

Silicon Austria Labs and EV Group Strengthen Collaboration in Optical Technology Research

Expanded collaboration includes installation of EVG’s LITHOSCALE® maskless exposure system, EVG®7300 UV-NIL system and complementary resist processing systems FLORIAN / GRAZ, Austria, November 13, 2023—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Silicon Austria Labs (SAL), Austria’s leading...

IMAPS 2023 Symposium Planned for October 2-5, 2023 in San Diego, CA

The 56th International Symposium on Microelectronics (IMAPS 2023) will be held October 2-5, 2023, at the Town & Country Resort in San Diego, California. This jam-packed, annual conference brings together industry engineers, researchers and top experts involved in advanced packaging and microelectronics assembly.  Given the strength of the program, many...

Challenges and Solutions for EDA of 3D Chip Stacks

It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits, such as for performance, functionality, and power consumption. Specifically, both design paradigms “More Moore” and “More than Moore” will benefit from 3D chip stacking (and new technologies and materials). 3D...

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

And what are we going to do about it in 2015…? A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again,...

3D processes and approaches: stepping stones to market adoption

I recently had one of those moments of clarity that comes from asking different people the same questions and fitting all the varied answers together like a puzzle to come up with the big picture. In this case, the questions had to do with the various approaches being developed to...

SEMATECH Technologists Detail Process Advances to Accelerate 3D Manufacturing Readiness

With a focus on providing cost-effective and reliable solutions to speed manufacturing readiness of 3D technology options, experts from SEMATECH’s 3D interconnect program based at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex outlined new developments in wafer bonding, copper removal, and wafer thinning at the 2010...