Package Designers Need Assembly-level LVS Signoff for HDAP Verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go.

Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move across the entire package to ensure proper connectivity and performance.

LVS SignoffWith its native support for packaging file formats, automated analysis of high-density advanced packaging connectivity verification requirements, and integrated assembly-level design rule checking and LVS signoff, the Calibre 3DSTACK tool provides a significant advantage over traditional system-on-chip LVS flow.

In this white paper, we look at some of the most common package verification issues, and how designers can use a solution like the Calibre 3DSTACK tool with automated package LVS capabilities to resolve them.