This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking.
In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead to warpage issues. The reason this is important is because through silicon vias (TSVs) communicate electrical signal, which makes warpage a critical assembly challenge.
Karimanal presented various unit processes and the role they play in overall process development. He talked about wafer-to-wafer (W2W), die to wafer (D2W), and chip-to-chip (C2C) stacks; three different underfill approaches; as well as reflow and thermocompression bonding. “All of these involve different temperatures, different materials, and different coefficient of thermal expansion mismatch (CTE). “ noted Karimanal.”To understand the thermomechanical implications, modeling is useful.”
For example, redistribution layers (RDL) add additional films to the thin wafer surface, ranging from 5-10µm, which is enough to cause CTE mismatch between the film and the substrate, causing warpage. This is exacerbated by margins in the assembly itself. Bumps need to be 50-25µm. How much allowable warpage is shrinking. In a foundry atmosphere, using modeling for the assessment of RDL and bumping and bonding options result in saved weeks and lower overall manufacturing cost.
“The warpage that really matters is the warpage at the time of assembly,” noted Karimanal. “3D stacking is a new area. Intuition only works to a certain point.”
There are thermo-mechanical model supply chain gaps, including characterization of materials, failure metrics and criteria, underfill characterization needs, and nonlinear material properties. Karimanal offered some suggested modeling solutions to this, that Cielution can provide. To find out more, the webinar recording is available here, and the accompanying slides are available here.