From the perspective of 3D integration and its march towards commercialization, there was not much new being presented at the 2015 IMAPS Device Packaging Conference and the Global Business Council (IMAPS DPC 2015) held concurrently in Fountain Hills, AZ, (March 16-19); at least not since the European 3D TSV Summit 2015, or 3D ASIP 2014 before that, or even GIT 2014, IWLPC 2014, and IMAPS International 2014 back in September.

If, like me, you attended all of the above, you experienced a number of repeat performances in both the keynote addresses and technology tracks; with at the most, incremental updates on product announcements and process optimizations. This is not the fault of the speakers or event organizers, its simply because, quite frankly, not much has changed in the past six months.

The big news in 2014 was that memory stacks are going into production, and that continues to drive optimization. In his keynote, Die Stacking is Finally Happening, Yuan Xie. Professor at UC Santa Barbara, explained why it has taken so long to move to die stacking, even though Intel first started created prototypes back in 2004, and demonstrated 3D memory architecture in 2007. Xie who was filling in for former Intel and AMD colleague, Bryan Black, AMD, reflected back on the last 10 years to offer perspective on why it’s taken so long to get here, and now that its here, how it will impact the market.

Essentially, he said the reason why die stacking didn’t take off between 2004 and 2007 was because it demonstrated only 10% improvement in latency over 2D, which wasn’t enough to justify the risk to go to 3D. “We needed to identify a novel architecture and a killer app,” he explained. “The technology may be feasible, but there are other factors to consider before it can be adopted.”

Xie described Intel’s “Tick Tock” business model, in which the first (tick) year, a product with a technology change is introduced, and the second (tock) year is when a new architecture is introduced. “When 3D integration is introduced, should it be a tick year, or a tock year?” since 3D involves both technology change and architecture change. Additionally, As Intel doesn’t have a DRAM business, they would have to engage a third party to custom-design a 3D DRAM stack.

That breakthrough came in 2014 with the introduction of the Knights Landing microprocessor, which integrates stacked DRAM from Micron, and targets high-performance computing applications. Rozalia Beica touched on this announcement as part of her keynote, Current and Future Technology Developments for High-End Applications.

Beica noted that while the driving forces are changing to wireless applications, the reality is that 57% of the market is still dominated by flip chip packaging. 3D IC and interposer integration make up 1% respectively, and fan-out wafer level packaging (FOWLP) has reached 3%. “Qualcomm has cautioned that interposers add substantial cost to the package, and without a significant reduction in cost, Si interposer-based packages will not be adopted into mobile applications,” she said.

Anything but TSVS
While there may not have been not much new to report in the formal presentations, there was lots of chatter about why that is. So I turned to the attendees and exhibitors to get their perspectives.

While TSVs are a well-established technology in image sensor, MEMS and RF applications, Ron Huemoeller, Amkor, says he thinks true 3D IC stacks are likely to be primarily a memory-play technology. Wilfried Bair, Tango Systems, says that while 3D IC with TSVs may be memory-play only, there are many options on interposers.

“TSV processes are ready,” noted Bair, “but the problem is they (the industry) keep finding other ways to improve performance, including through software programs.” Bair also disagrees with the notion that that the cost of future scaling is prohibitive, and that that will drive the industry to 3D ICs. While he acknowledges that the cost of designing mask sets and lithography processes at smaller nodes is higher, he says we need to look at the individual cost of the die, which is not higher. “It hasn’t proven to be true at 22nm or 14nm, according to the companies working at lower nodes,” he said.

Matt Nowak, Qualcomm, also said TSVs are ready to go. “We’re just waiting for the right application for them that can bear the high cost.”

In the mean time, the latest trend at the OSATS is to find a way around TSVs, because of the cost and difficulty in design. Jan Vardaman says if they can find a way to do it without 3D TSVS they will.

At IMAPS Interntional 2014 in San Diego, Xilinx and SPIL introduced a silicon-less interposer technology (SLIT) that eliminates the need for TSVs by forming the interconnect between the microbump an 65nm Si interposer. Phil Garrou described it here on Insights from the Leading Edge. TSMC has also rolled out a simplified and lower-cost version of its chip-on-wafer-on-substrate (CoWoS) technology, called integrated fan-out wafer level (InFO) technology. They have also developed a 3D package-on-package (InFO-POP) version of the technology, which involves a wire-bonded DRAM packaging on the top layer.

At IMAPS DPC 2015, Amkor threw its hat into the silicon-less, TSV-less ring with the introduction of its silicon-less integrated module (SLIM) technology. The significance of this when compared with other options is that, according to Ron Huemoeller, they have achieved .5µm line and space.

Mike Kelly, Amkor, presented the new technology. He explained the process flow, in which die are flip-chip attached side-by-side on a silicon carrier that has and RDL layer on it using micro Cu pillar technology. After standard reflow, the wafer is over-molded, then flipped. The silicon is completely removed down to the RDL by back-grinding, followed by a silicon etch process. Multiple die can be attached. There is no interposer involved, and no TSVs. While there is still a temporary bond/debond step, it is much simpler, and there is no need for plasma-enhanced physical vapor deposition (PEPVD) or chemical mechanical planarization (CMP) steps, because there are no TSVs to reveal.

According to Matt Nowak, all of these alternative technologies- SLIM, SLIT and InFO, will have a place in high-performance computing at a lower cost than TSVs.

With regard to monolithic 3D IC, another TSV-less stack-up approach using front-end processes, which was discussed at length at DATE 2015, Nowak said that at Qualcomm its an R&D project which, while it has promise, is years out. “People are excited about the prospect of it, but It’s even more difficult to design than 3D ICs. There are no tools,” he said.

TSVs in Volume?
Not everyone agrees about the definition of ‘volume production.’ There are many who are still enthusiastic about 3D TSV as a volume application. It depends on “if you measure volume in billions of parts or billions of dollars,” quipped Lee Smith, UTAC. In other words, high-performance applications, even in low volume, can bring in the dollars that qualify TSVs to be considered high volume processes. Sitaram Arkalgud, Invensas, also pointed out that the applications using TSV, when considered together, have considerable volumes. “TSVs is a HUGE market.” He said, pointing out that most smartphones have not one, but 2 cameras that require images sensors with TSVs. Most people have more than two devices that contain TSVs. “Memory is just the tip of the iceberg,” he noted.

So hang in there, 3D TSVs, we’re not giving up on you yet. There will be more to talk about before you know it. ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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