In my previous post I talked a bit about the ongoing debate that went on during last week’s Global Interposer Technology Workshop (GIT 2014) which took place at Georgia Tech’s Global Learning Center. Do we wait for the “trickle down” effect to take place and bring the cost of interposer and 3D ICs down, or do we create a consortium to focus on developing low-cost interposer solutions?
In his keynote, “(Interposer) and 3D Integration, Where we’ve been, Where we are and Where we’re Going,” Qualcomm’s Riko Radojcic talked about Gartner’s Hype Cycle, and how, thanks to Xilinx’ FPGA on interposer modules and memory stacks now in production, we’re now on the plateau of productivity, but risk slipping back to the “trough of disillusionment” due to “unfulfilled promise” of lowering cost for both Wide I/O memory on logic, and spit die logic on interposer stacks.
He’s concerned that we’re experiencing “Zeno’s Paradox” in which the quickest runner can’t ever over take the slowest in a race if the slowest was given a head start. “By the time a technology is deployed the requirement has moved,” he explained. In other words, technology development can’t be driven by the product requirement. “To leverage a disruptive technology, the product must be architected for it,” he said. He suggested we take the approach as an industry to define and use “concept architectures” analogous to building “concept vehicles” for our space, and drive R&D on the selected technology. Low cost packaging is the key, and one of the vectors would be how cheap can we make the package through, for example, large panels, mass reflow, and self alignment. “We need to drive the roadmap and R&D efforts to get the cheapest package.” Or alternatively, we need to come up with a value-added interposer with embedded diodes, capacitors and inductors, which would reduce overall system cost.
His vision is an R&D consortium with a pilot line infrastructure that focuses on packaging-based more-than-Moore (MtM) technology enablers. It will have state-of-the-art equipment and materials that are consistently upgraded, with professional, permanent leadership staff to design vehicles, build samples, and perform analyses. It would have tight IP policies, a tight business model, separate identity, vision and roadmap with deliverables and accountability. “There is no such thing in low-cost packaging today,” said Radojcic. “It would be a graceful runway for deploying disruptive package-based, ‘More than Moore’ technologies.”
Qualcomm is known for having focused its efforts on the self-defined Wide I/O 3D through silicon stack (TSS). The company has targeted full 3D directly rather than interposer packages because interposers themselves are so costly, and the company is adamant about a low-cost solution. “We used to believe that (interposer) technology was too big for a phone. Now we think (interposers) can go into phones,” he said; if a low-cost solution can be developed in a timely manner.
Every year, Qualcomm performs analyses between current package-on-package solutions and TSV-based interposer solutions. So far, Radocjic says the value proposition to make the shift hasn’t been compelling enough for Qualcomm. Matt Nowak, Qualcomm, agrees that the company won’t go to Interposer with TSV until the price comes down.
The flip side to solving the issue of low-cost interposer technology is just to let things play out naturally, in a “trickle down” approach; the theory being that as equipment depreciates and high-end application volumes increase, the cost of these devices will come down and be adopted in mobile applications.
Peter Chen, Xilinx, says he believes the industry will invest in interposer and 3D technologies, and price will come down. Ron Huemoeller, Amkor, agreed, noting that investments have been made and the ROI pressure is there. The manufacturing lines have been in place long enough to start realizing depreciation benefits.
While many agree that there is a value-add to interposer devices, Huemoeller says the are unlikely to see a better profit margin on these products vs. previous products. “Margins hold across packaging technology,” he said. “This one will be at the higher end of the packaging margins, but won’t exceed what we normally see.”
While the trickle down approach worked with taking flip chip technologies mainstream, Chen pointed out that the difference here is that adopting flip chip was a packaging issue, and with interposers we’re running into design issues. “Partitioning needs to be redesigned – people aren’t thinking about the architecture of the chip, but its an important part,” he said. “The elements need to be there to have volume development.” Areas with room for improvement include 3D IC design and verification methodology, and EDA Tools. “Circuit designers face similar design and verification challenges in interposer design as do package designers.”
It depends on the courage of designers, noted Huemoeller. SOC partitioning is a different structure. “It really is ready for designers,” he said. “They’ll see that this is a safe area for package solutions today.”
Despite the high cost of interposer technologies, what is now happening is what we’ve been saying for years; interposers and 3D will happen when there’s no other way to do it.
In her talk, The Year of The Interposer, Jan Vardaman, TechSearch International, said the interposer era has arrived. Xilinx, the first to go to production with interposers for FPGA products back in 2012, now has six products using interposers. There are ASIC designs, and GPU plus stacked high bandwidth memory (HBM). “The cost-benefit analysis allows them to adopt an interposer solution because they can’t get the performance any other way,” said Vardaman. “They’re low volume units, but high dollar volume.”
The time has also come for Memory and is around the corner for GPUs. Jangseok Choi, Samsung, talked about how the company is transforming memory with TSV, driven by virtualization, cloud, big analytics, power, performance and capacity. Samsung’s first TSV product is its 64GB RDIMM. He said the 3D DDR4 architecture couldn’t be done without TSVs. “We can put all the unnecessary circuitry in the slave chips, and the communication in the master die on the bottom to reduce the power of the internal operation,” he said. Samsung’s biggest challenge with bringing out stacked memory was cost. “The back-end needed specialty handling equipment, and we needed a good justification for the future potential of market to make investment in the specialized wafer handling equipment,” said Choi. Now there is justification, so they are moving forward.
With claims that “SK hynix will be the first memory supplier who jumps into the lake of TSV mass production,” Minsuk Suh explained that HBM with an interposer is a solution for bandwidth hungry processors. He reports that the company qualified HBM internally in September 2014 and shipped samples to customers in October 2014. They also produced an engineering sample of WIO2 in September 2014, and have customer samples for HBM networks and graphics. He also said the plan to have engineering samples of a 3D stacked main memory product in February 2014.
Will 3D stacked memory drive the interposer business? Micron’s Dean Klein says yes. ”My belief is that the memory/CPU interface is one application that can drive interposer business forward.” Phil Garrou noted that without memory stacks, people haven’t been able to do designs and move forward. “We now have memory stacks in production.”
nVidia’s Abe Yee described the architecture of Pascal, the company’s GPU targeted for 2016 production, that will be interposer based, with high capacity 3D Memory surrounding the GPU. Yee said while the computing requirements for GPU performance will continue to scale, it will need the high capacity of 3D HBM to function properly.
According to Vardaman, the top ten fabless companies investigating, planning to use, or using interposers for advanced packaging include the aforementioned Qualcomm, Xilinx, and nVidia, as well as Broadcom, AMD, Mediatek, Marvell, LSI, Altera and Avago. She predicts however, due to its sensitivity to cost, Qualcomm will go into fan-out wafer level package (FOWLP) first.
In addition to interposer technologies, parallel developments in advanced PoP, TSV-less approaches have been ongoing, and may be targeted to Qualcomm’s demand for low-cost solutions. Will this push out interposer/3D TSV adoption in mobile products? Not necessarily. Other mobile manufacturers that have internal ability (Samsung) may implement 3D because they can absorb the cost. Apple is another example. Vardaman pointed out that the company seems to be able to maintain a high margin, thanks to so much demand for its next-gen products that consumers line up outside the stores and camp for days waiting for the product launch.
So which path is the best to take to lowering the cost of interposer packages? A natural progression or a concerted consortium effort? Maybe the solution will come from some place we haven’t considered yet. That’s what Jeff Burns, PhD, Director, IBM VLSI Research, thinks will happen. He said usually when a capability becomes viable it allows something you didn’t have before to be developed by someone you don’t know. “It’s a bit of a fool’s errand to run after applications,” he said. “Its not going to come from existing players doing existing things. Wifi, Google, Cloud computing didn’t come from IBMs doing something incrementally better. It’s very hard to pick a future application and drive the technology to that.”
At the close of GIT 2014, Nowak delivered his summary in the form of a survey for the attendees to take in the coming days and return to him. Two of the agree/disagree statements have to do with the debate discussed here. I will be curious to see how many agree that the cost will – indeed already is – coming down for interposer technologies, vs. how many think a consortium is needed to focus on developing these solutions. Readers, based on what I’ve outlined here, what do you think about this? Comments, as always, are welcome! ~ F.v.T.