Monolithic 3D IC Heats Up at DATE 2015

Monolithic 3D IC Heats Up at DATE 2015

Despite the fact that monolithic 3D IC is still very much in development stages, its promise to gain a full node in terms of power and performance while eliminating the need for TSVs, gained it “Hot Topic” status at this year’s Design and Test Europe (DATE 2015) which took place in Grenoble, March 9-13, 2015, with an entire session of design-focused presentations devoted to it.

Monolithic, or sequential, 3D IC is described as a build-up process to fabricate vertical layers of transistors on the same starting substrate using nano-scale inter-layer vias as interconnects, rather than stacking substrates and interconnecting them with TSVs. In this way, researchers believe that logic and memory can be integrated, as well as logic on logic, and other functions.

While the concept of monolithic 3D IC has been discussed for years, it wasn’t really considered feasible until the development of Leti’s CoolCube technology, which uses a cold layer build-up process that eliminates the need for high temperatures that could degrade the performance of transistors or metal interconnects between the layers.

The DATE 2015 session, Monolithic 3D: A Path to Real 3D Integrated Chips, looked at design considerations for various applications. We heard first from Olivier Billoint, CEA Leti, who discussed monolithic 3D cell design using 2D tools. “We’re able to do it, but we’re trying to motivate the EDA people to make a 3D place-and-route tool,” said Billoint. Essentially, the 2D tool showed that it’s feasible by design and methodology, but commercialization requires a 3D tool. When asked when they would need such a tool, he responded that in 2 years, they would be ready for tape out.

This illustration represents the four-layer prototype high-rise chip built by Stanford engineers. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic “elevators” that connect logic and memory, allowing them to work together to solve problems. Credit: Max Shulaker, Stanford

This illustration represents the four-layer prototype high-rise chip built by Stanford engineers. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic “elevators” that connect logic and memory, allowing them to work together to solve problems. Credit: Max Shulaker, Stanford

Max Shulaker, Stanford University, detailed efforts in designing monolithic 3D ICs using carbon nanotube (CNT) structures vs. silicon. He described a wafer-scale low-temperature CNT transfer processes that can be done at 120℃; even cooler than the CoolCube. He described a demonstrator that uses this process based on 2D techniques to build a so-called “high-rise chip” that sandwiches 2 RRAM layers between 2 logic layers. The process is Si CMOS compatible, said Shulaker, in that the Si FETS can be used to build only the bottom layer, because of the high temperatures required for subsequent Si layers. In this design, the next layers are fabricated with CNT layers. Shulaker claims the high-rise chip enables us to realize abundant data applications due to active on-chip data and computation immersed in memory. The density achieved by monolithic 3D nanoscale interlayer vias is 1000x that of TSVs. Additionally, as there are no bonding required, there’s no issue with bonding inaccuracies.

The final presentation from Pierre-Emmanuel Gaillardon, EPFL, described an ultra-low power FPGA design based on monolithically-integrated RRAMS. He described a back end of line (BEOL) integration process to achieve high-density integration. This design merges RRAM with that data path that’s used to perform logic operations in FPGAs. This technology isn’t about achieving smaller size devices, but rather an unconventional use of novel memory technologies. “Better devices don’t mean smaller devices,” noted Gaillardon.

From a design perspective, it appears that monolithic 3D ICs are a more attractive option than TSV based 3D IC stacks because there’s no need to be concerned with keep-out-zones and TSVs going through active circuitry. Even though there is a call for 3D EDA place and route tools, it appears design methodology may not be all that different than 2D design. It will be interesting to see whether the progress to manufacturing will be more accelerated than TSV based 3D ICs have been. ~ F.v.T.