ET-Stacked-Die-SolutionProduct Description
Cadence Encounter Test provides a comprehensive methodology for 3D-IC design-for-test and automatic test pattern generation that includes a DfT architecture that controls and observes an individual die from the chip I/Os, different test modes to control application of tests up and down the stack, and interconnect tests to detect through-silicon via defects.

This product has contributed to the advancement of 2.5D and 3D IC manufacturing by enabling a comprehensive manufacturing test methodology to validate logic-on-logic and memory-on-logic die stacks at each step of the assembly process; including pre-bond, post-bond, and post-packaging steps. The test methodology development is a joint collaborative effort between Cadence, imec, and TSMC. A testament to this product is its use on a TSMC Chip-on-Wafer-on-Substrate (CoWoS™) test chip using the JEDEC Wide-I/0 mobile DRAM interface. The design of the test chip is a 3D stacked IC which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The validation results show that the silicon area of the additional DfT wrapper is negligible compared to the total logic die size (<0.03%). Moreover, the test pattern generation was very efficient (tens of patterns, generated in only a few seconds) and effective (100% coverage of the targeted faults). Relevant references can be found here.


Francoise von Trapp

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