I’ve got two questions for readers, based on recent headlines from TSMC.
First of all, are TSMCs activities in building out capacity for 3D ICs spurring leading Taiwanese assembly and test houses to increase capacity as well? That’s what’s implied in this news item on CENS.com, which reports that ASE, SPIL and Powertech are all investing heavily in 3D IC R&D manufacturing and capacity. (the fact that these OSAT powerhouses are investing in 3D is not news, but the inspiration for this investment is!)
At first read, you might think that the assembly houses are adding capacity in hopes of capturing TSMC back-end business. But that’s unlikely to be the case, since TSMC has been very vocal about providing end-to-end 3D IC manufacturing. According to the article, IC assemblers say that although TSMC has begun deploying 3D IC packaging capability, it provides the service as a total solution to only high-end customers such as Apple. So it’s more likely that these top tier OSATS are positioning themselves to work with other foundries such as UMC and GlobalFoundries in a collaborative model to provide a viable alternative 3DIC solution to TSMC, and likely at a lower price point.
TSMC has also been making headlines (EE Times) (Electronics Weekly) with its concept of operating single customer fabs so they can better accommodate the supply demands of their larger customers such as Qualcomm. (Except that David Manners reported here in his Electronics News Weekly blog, Mannerisms, that Qualcomm is thinking of buying a 10% share in UMC to secure advance IC fabrications.)
However on Hothardware.com, blogger Joel Hruska, implies that it’s Apple’s business that is the key motivator (even though TSMC has not made any statements to that effect). Hruska goes on to theorize how this arrangement would make sense for Apple, while wreaking havoc on TSMC’s other customers, and perhaps explains why Qualcomm is looking to buy into UMC.
So here’s what I’ve been pondering. If TSMC follows through on this idea, will that be front-end fabs only? Or are they going to include their 3D IC operations (which involve mid-end processing, assembly and test) in that model as well? Because that would be a pretty major investment to add all that 3D IC capacity. Readers, any thoughts on that? ~ F.v.T.