The Golden Age of Packaging Brought to you by Chiplet IntegrationMar 16, 2020 · By Francoise von Trapp · Blogs When people weren’t talking about the coronavirus at this year’s 2020 IMAPS Device Packaging Conference and its co-located Global Business...
IEDM 2019: Innovative Devices for an Era of Connected IntelligenceDec 16, 2019 · By Dean Freeman · Blogs The IEEE International Electronic Devices Meeting (IEDM) been one of my favorite conferences for many years. Early in my career,...
IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet StandardizationDec 05, 2019 · By Phil Garrou · Blogs In 2017, AMD used chiplets in their “Zen 2” architecture to develop the Epyc server processor “Naples” (Figure 1). AMD...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die IntegrationNov 25, 2019 · By Phil Garrou · Blogs Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!Nov 13, 2019 · By Phil Garrou · Blogs Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...
IFTLE 427: TSMC’s Next-Gen 3D Technology – N3XTOct 11, 2019 · By Phil Garrou · Blogs Continuing our look out into the future, at the recent Hot Chips Conference, Dr. Phil Wong, VP of R&D at TSMC...
A Look at US Investments in Heterogeneous IntegrationSep 24, 2019 · By Herb Reiter · 3D In Context The semiconductor industry is not only very capital-intensive, but investors experience very long payback times. Both limit the availability of...
IFTLE 423: GLOBALFOUNDRIES and ARM Turn to 3D Chip Stacks for High Performance ComputingAug 21, 2019 · By Phil Garrou · Blogs It was exactly a year ago that GLOBALFOUNDRIES’ announced that they would no longer be competing in the node scaling...
IFTLE 400: Intel Logic-Logic 3DIC and Chiplets are Finally HereDec 14, 2018 · By Phil Garrou · Blogs At the Intel “architecture day” held Dec 12th in Santa Clara, Intel finally announced what some of us have been...
IFTLE 396: DARPA Envisions CHIPS as New Approach to Chip Design and ManufacturingOct 17, 2018 · By Phil Garrou · Blogs First a word on the change in venue… After working with Pete Singer at Solid State Technology from 2010-2018 and...
Striking the Right Chord for Chiplet IntegrationJul 30, 2018 · By Amin Shokrollahi · 3D In-Depth The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution...
The 14th 3D ASIP Conference Addresses a Spectrum of 0pportunities, Part 1Jan 09, 2018 · By Herb Reiter · 3D In Context Several years before I started promoting 3D IC benefits in 2008, a small team of industry visionaries founded the 3D...
The Truth About Moore’s Law is Revealed at 3D ASIP 2017Dec 11, 2017 · By Francoise von Trapp · Blogs I’ve long held the belief that when it comes to reading scholarly works, very few people read the entire paper....
System-level Scaling: UCLA’s Answer to Extending Moore’s LawNov 11, 2015 · By Francoise von Trapp · 3D Event Coverage “We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make...