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Dr. Cliff Hou, Senior Vice President and Deputy Co-COO (above), spoke at this year’s 2025 Technology Symposium. highlighting TSMC’s continued advancements in manufacturing technology and global capacity expansion, including updates on new facilities in the United States, Germany, and Japan. Dr. Kevin Zhang SVP, Business Development and Global Sales, and...
Continuing our coverage of ECTC 2021, let’s take a look at the session on Heterogeneous Integration (HI) using 2.XD/3D packaging, chaired by Subash Shinde of Notre Dame and John Knickerbocker of IBM. IBM Introduces Direct Bonded HI Si Bridge Technology Though they are not manufacturing chips or packages anymore, IBM...
Equipment Communication Leadership in Wafer Fabrication For many years the semiconductor industry’s wafer fabrication facilities, where semiconductor devices are manufactured on [principally] silicon substrates, have universally embraced and mandated the GEM standard on nearly 100% of the production equipment. This includes the complete spectrum of front-end-of-line (FEOL – device formation)...
In previous posts, I discussed a process for process-centering a design. In this post, we will examine how non-robust design’s erratic yields can impact the manufacturing environment and cost of a product. A non-robust design will have at least one specification that is skewed away from the specification’s center as...
I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for...
Eric Beyne (imec) and I go way back. He’s the Scientific Director of Advanced Packaging Technologies at imec, and ever since my Advanced Packaging days, he’s been a valuable resource whenever I have technology questions about any part of the spectrum of 3D integration technologies. Basically, I can count on...
Tish LeBlanc, from TI: "How's your SEMICON West going? Me: "I was just trying to put it into words." It's Thursday, and another SEMICON West (my seventh) is winding down, and its the first time I've found time to write since Monday evening. As always, it's been a whirlwind of...
Ever since I put on the editorial director hat for 3D-ICs.com, which aggregates 3D technology news, blogs and papers, and categorizes them as either TSV and 3D packaging or monolithic 3D, I’ve been trying to wrap my head around the differences between 3D TSVs and monolithic 3D integration technologies. I’ve...
Semiconductor test and advanced packaging service provider (SATS) STATS ChipPAC announced it has has expanded embedded Wafer-Level Ball Grid Array (eWLB) technology -- jointly developed by STATS ChipPAC, Infineon, and ST Microelectronics -- to reconstituted 3
EV Group (EVG) and Applied Materials, Inc. announced a joint effort to develop wafer bonding processes for the manufacture of TSVs for 3D IC packaging applications. The two companies will be working together as members of the EMC-3D Semiconductor 3D...
